[SI-LIST] Re: DDRII write problem!!

  • From: Heyfitch <heyfitch@xxxxxxxx>
  • To: TinaWu <tinawu@xxxxxxxxxxx>
  • Date: Tue, 18 Aug 2009 23:05:15 -0500

To elaborate on my previous message, that may be too concise.....
Whenever the enable node is pulled so that the buffer is a driver, the
internal node "nd_out_of_in" becomes 0.5V - i.e. half way between the core
logic high and low. This makes me think that you may not be explicitly
controlling the EN node of the buffer and it flaps cack and forth between
high and low causing the buffer to alternate between  being a receiver and a
driver. At the times when it's a driver, this node goes 0.5V.
- Vadim Heyfitch
On Tue, Aug 18, 2009 at 10:43 PM, Heyfitch <heyfitch@xxxxxxxx> wrote:

> Tina,
> the info you gave is not sufficient to unambiguously tell what the problem
> is. It is possible that you are not controlling 'enable' pin of the buffer
> on the DRAM model. You need to state appropriately to be receiving.
>
> Vadim
>
> On Tue, Aug 18, 2009 at 9:38 PM, TinaWu <tinawu@xxxxxxxxxxx> wrote:
>
>> Dear Sir,
>>    I simulated the DDR write and the waveform is bad.
>> Here, I found the input(DQ) of DDR chip.
>> There are 3 states - logic 0 (0V)ã??logic 1 (1V) and
>> the other state 0.5V. Is the phenomena right??
>> Thanks in advance!!
>> BRs,
>> Tina
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