Hung,
Since your questions are somewhat specific to HyperLynx SI, I think you will
get more specific answers from Mentor. I suggest you open a service request so
that you can communicate privately about the details of your design and models.
For this open forum, here are few general answers.
1. HyperLynx SI uses whatever package model you have defined in the IBIS model
that you assign to components in the design. If you want pin specific package
model, then {R, L, C}_pkg parameters are not sufficient. The IBIS model needs
{R, L, C}_pin parameters or [Package Model].
2. Generally, the connector is expected to be included in the EBD data. Mentor
support might help you with your specific model data.
3. Timing of the DDR controller is specific to each controller. You need to get
the timing information from the controller vendor, and then it is fairly easy
to get that data into a component-specific timing model. See the HyperLynx tool
documentation or related articles on Mentor Support Center.
4. The DDR wizard can be configured to include many SI effects, and save the
waveforms. You can review the waveforms after the wizard runs. Another option
is to run the DDR bus nets in the batch SI simulator, and then review the
simulator report or resulting waveforms.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Hung Dang
Sent: Wednesday, November 1, 2017 6:18 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR4 timing analysis with Hyperlynx
Dear Expert,
I am a newbie in SI study. So I'm looking forward to hear the any
recommendations from the experts. My problem is below:
I use the DDRx batch-mode in the Hyperlynx to analyze timing, SI and Xtalk of
DDR4 interface. I have done the post-layout phase and export the results such
as timing, eye diagram...But I have some confusions and need the explanations
or recommendation from the experts.
1/. At the DDR controller, I have assigned the IBIS model. But IBIS model does
not count the pin delay (trace length in the package) in the chip package while
the match length of DDR traces in PCB have counted these pin delay (it's
established in the allegro constraints). Does this make the error in the
timing results ? If yes, can you show me how to assign the trace length in the
package to simulation system?
2/. At the DDR DIMM, I have assigned the .EBD model for DIMM. It mean I have
not counted the loss on the DIMM connector. How to assign the DIMM connector in
this situation?
3/. DDRx batch-mode in the Hyperlynx need the timing model for controller and
DIMM. With DIMM, I can get timing the parameter from datasheet or DDR4 JEDEC
standard. But with controller, I have not enough the spec to get timing
parameter, so I use the default timing model exist in the hyperlynx.
Can I verify the DDR4 routing in the PCB with this default model ?
4/. What are the kind of DDR4 simulations to verify DDR4 routing in the PCB ?
Thank you so much.
--
Thanks & Best Regards
Hung Dang
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