Dear Hung,
Below is my opinion for only reference.
Maybe other specialists do agree or not.
1. About pkg time delay.
In the IBIS model, there might be Rpin Lpin Cpin.
If you have it, you can simulate with this parameter after making
series R-L-C circuit in your simulator.
Or roughly you can calculate the pkg pin delay like sqrt(Lpin X Cpin)
2. About DIMM connector
If you can get the modeling data like spice format which is extracted
by quasi-static solver such as Q3DE, you might be able to
assign the spice netlist into DIMM. I am not sure that Hyperlynx can
support it or not.
3. Controller's timing spec.
Generally DDRx IP in controller uses jedec standards.
So how about using your memory spec. when the memory stage is on
driver, that means READ mode.
Also, DDRx has synchronous clock system, that means it is possible to
be spec. in if the all propagation delays are very close to each
others.
Of course this propagation delay is not always same with trace length.
4. DDR4 consideration at PCB
In my case, I will consider signal quality, cross talk, timing and
power integrity.
SSN will help us to get signal quality, cross talk and timing.
AC analysis power integrity.
Of course the PDN of IC and the spice netlist will be greatly helpful
to increase the simulation accuracy.
Sincerely,
Inmyung Song
2017-11-01 21:17 GMT+09:00 Hung Dang <dmarc-noreply@xxxxxxxxxxxxx>:
Dear Expert,
I am a newbie in SI study. So I'm looking forward to hear the any
recommendations from the experts. My problem is below:
I use the DDRx batch-mode in the Hyperlynx to analyze timing, SI and Xtalk
of DDR4 interface. I have done the post-layout phase and export the results
such as timing, eye diagram...But I have some confusions and need the
explanations or recommendation from the experts.
1/. At the DDR controller, I have assigned the IBIS model. But IBIS model
does not count the pin delay (trace length in the package) in the chip
package while the match length of DDR traces in PCB have counted these pin
delay (it's established in the allegro constraints). Does this make the
error in the timing results ? If yes, can you show me how to assign the
trace length in the package to simulation system?
2/. At the DDR DIMM, I have assigned the .EBD model for DIMM. It mean I
have not counted the loss on the DIMM connector. How to assign the DIMM
connector in this situation?
3/. DDRx batch-mode in the Hyperlynx need the timing model for controller
and DIMM. With DIMM, I can get timing the parameter from datasheet or DDR4
JEDEC standard. But with controller, I have not enough the spec to get
timing parameter, so I use the default timing model exist in the hyperlynx.
Can I verify the DDR4 routing in the PCB with this default model ?
4/. What are the kind of DDR4 simulations to verify DDR4 routing in the PCB
?
Thank you so much.
--
Thanks & Best Regards
Hung Dang
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