[SI-LIST] Re: DDR3 output timing uncertainty question.

  • From: Ken Patterson <ken.patterson@xxxxxxxxxxxxx>
  • To: "Nitin_Bhagwath@xxxxxxxxxx" <Nitin_Bhagwath@xxxxxxxxxx>
  • Date: Tue, 25 Aug 2015 20:52:02 -0400

For write transactions use the average of tdqsdq(min) and tdqsdq(max).
These values can be found in the data sheet or timing model for your chosen
memory speed.
Ken

On Tuesday, August 25, 2015, Bhagwath, Nitin <Nitin_Bhagwath@xxxxxxxxxx>
wrote:

Hello Dave,

During read transactions, tDQSQ gives the latest valid output transition
time of a DQ with respect to its strobe. tQH gives the earliest that the
output DQ can go invalid with respect to its DQS.

These two together should describe the output valid (and invalid) timing
between DQ and DQS, and hence the output uncertainty between them.

Regards,
-Nitin

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx <javascript:;> [mailto:
si-list-bounce@xxxxxxxxxxxxx <javascript:;>] On Behalf Of David Banas
Sent: Tuesday, August 25, 2015 4:05 PM
To: si-list@xxxxxxxxxxxxx <javascript:;>
Subject: [SI-LIST] DDR3 output timing uncertainty question.

Hi all,
How does one estimate the relative output timing uncertainty, between DQ
and DQS, for a DDR3 SDRAM part, from its data sheet?

Thanks,
-db


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Ken Patterson
Principal Hardware Engineer
Netronome
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