[SI-LIST] DDR3 output timing uncertainty question.

From: David Banas <DBanas@xxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Tue, 25 Aug 2015 23:04:45 +0000

Hi all,
How does one estimate the relative output timing uncertainty, between DQ and
DQS, for a DDR3 SDRAM part, from its data sheet?

Thanks,
-db

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[SI-LIST] DDR3 output timing uncertainty question.

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