[SI-LIST] DDR3 Rx design
- From: rahul kumar <rahul05kumar@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 16 Jul 2010 23:26:47 -0700
Hello,
One questions about DDR3 IO Rx design ( DQ / CA ). Standard mentions
minimum high / low time of 360pS at receiver's input in 1600 speed bin. This
means, Pseudo receiver design is to be targeted to work at ~1388Mhz
frequency with worst case swing of Ref +/- 150mV. Is my intrepretation
correct ?
Kindly help.
Thanks & Best Regards,
Rahul.
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