[SI-LIST] Re: DDR3 Rx design
- From: steve weir <weirsi@xxxxxxxxxx>
- To: rahul kumar <rahul05kumar@xxxxxxxxx>
- Date: Sat, 17 Jul 2010 00:27:49 -0700
1600Mbps = 667ps / bit cell >> 360ps
Steve.
rahul kumar wrote:
> Hello,
> One questions about DDR3 IO Rx design ( DQ / CA ). Standard mentions
> minimum high / low time of 360pS at receiver's input in 1600 speed bin. This
> means, Pseudo receiver design is to be targeted to work at ~1388Mhz
> frequency with worst case swing of Ref +/- 150mV. Is my intrepretation
> correct ?
>
>
> Kindly help.
>
> Thanks & Best Regards,
> Rahul.
>
>
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--
Steve Weir
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