[SI-LIST] DDR3 Diff Signals Slew-rate
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 18 Feb 2010 14:38:58 +0200
Dear Experts
The Derating Tables & Figures in the DDR3 JEDEC (JESD79-3D), define a
"nominal slew-rate" for the Address/Command/Data signals.
I couldn't find any such reference to the diff signals - CLK & DQS.
Is the reason for this is that the diff signals are not allowed to have
a slew-rate which is different from the "nominal" one?
I hope my question is clear enough, but I'll try to clear it further:
When looking at the above mentioned figures (e.g. Fig. 110), one can see
that the slew-rate of Single-ended signals is allowed by the spec to be
non-constant, and therefore the definition of the "nominal slew-rate"
arises.
My question is, therefore: Are the Diff signals not allowed to have such
a non-constant slew-rate? Are they required to have a constant
slew-rate?
Thanks
Itzhak hirshtal
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