[SI-LIST] DDR3 DQ-DSQ skew over temperature
- From: Boris Bakshan <bbakshan@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 7 Jan 2015 15:05:08 +0200
Dear all,
In read leveling procedure DQS and DQ signals are aligned in the controller
so that optimum phase shift between the signals is achieved.
What happens on temperature and voltage drift?
If the read leveling calibration was originally performed at 0 degrees and
-5% of VDD/VDDQ and certain optimal values had been concluded then if
temperature now rises to 85C and voltage +5% *then it might not be optimal*
since tDQSQ and tDH might have changed (and probably timing parameters of
the controller had also changed).
How is this being settled?
Is it common to re-perform read leveling with temperature and voltage
changes?
Thank you.
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