[SI-LIST] Re: DDR3 DQ-DSQ skew over temperature

  • From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 07 Jan 2015 19:26:49 +0100

Hello,

the output timings are aligend by the DLL circuit on the DRAM. this
should compensate Voltage/process/Temperature changes and align DQ/DQS
to the incoming clock.

In addittion both output circuits DQS and DQ should heat up by the same
amount, so the timing of both would change and especially DQS vs. DQ
timings should stay anyhow the same..

Hermann

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Hermann Ruckerbauer
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Am 07.01.2015 um 14:05 schrieb Boris Bakshan:
> Dear all,
> In read leveling procedure DQS and DQ signals are aligned in the controller
> so that optimum phase shift between the signals is achieved.
> What happens on temperature and voltage drift?
> If the read leveling calibration was originally performed at 0 degrees and
> -5% of VDD/VDDQ and certain optimal values had been concluded then if
> temperature now rises to 85C and voltage +5% *then it might not be optimal*
> since tDQSQ and tDH might have changed (and probably timing parameters of
> the controller had also changed).
> How is this being settled?
> Is it common to re-perform read leveling with temperature and voltage
> changes?
>
> Thank you.
>
>
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