[SI-LIST] DDR3 Clock non-monotonicity issue
- From: Bala G <bala89si@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 7 Feb 2013 17:00:03 +0530
Hi Experts,
I am doing simulation and measurement for DDR3 interface operating at
1866MT/s in one of our fabricated board. We have 5 DDR3 (4-DDR & 1- ECC)
SDRAM chips in the Daisy chain. When I simulated for clock and probed at
pin of the first DRAM in the Daisy chain, the clock was highly
non-monotonic and this non-monotonicity decreases down the line of daisy
chain. When I did the measurement to validate the simulation using
Tektronix 12GHz differential probe at the first DRAM test points the signal
doesnt have the non-monotonicity issue. I am not sure what is causing the
problem, whether its an issue with IBIS Model or any. Btw I checked for
different clock drive strengths but the problem still exists. Any valuable
suggestion will be helpful for me to align the simulation & measurement.
Regards,
Balaji
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