[SI-LIST] Re: DDR3 Clock Signal
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: "Jennifer Maharani" <jennifer.maharani@xxxxxxxxx>, "si list silist" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 11 Jun 2010 07:58:45 -0600
Jennifer,
The controlling document is JESD79-3D (I think that's the latest one). It
will answer all of your questions. Go to jedec.org and search on DDR3.
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jennifer Maharani
Sent: Friday, June 11, 2010 6:22 AM
To: si list silist
Subject: [SI-LIST] Re: DDR3 Clock Signal
Many thanks Hermann. So the swing is indeed 3.0V, right?
On Jun 11, 2010, at 10:52 AM, Hermann Ruckerbauer
<hermann.ruckerbauer@xxxxxxxxxxxxx
> wrote:
> Hello Jennifer,
>
> you can look at the Clock drivers as two single ended Drivers (both
> driven with 1.5V).
> If you look at it from receiver side: The normal single ended Signals
> (DQ and CA) are comparing the input signal against Vref. Due to the
> differential comparison of the clock receiver the input swing (and
> slew
> rate) that the diff RX will evaluate (CLK-CLKb) is double the single
> ended RX swing (Signal - Vref).
>
> regards
>
> Hermann
>
>
>
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb Jennifer Maharani:
>> Dear all,
>>
>> I found that the supply voltage of DDR3 is 1.5V. How is this realized
>> for the differential clock. Is it using two single-ended 0.75V or one
>> differential 1.5V ?
>>
>> Many thanks,
>> Jenni
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