I am using a Virtex-4 FPGA in a new design. I have provided two sodimm connectors. I am using 2T (common address and command bus)topology. I tried simulating it with 2GB SODIMM modules from micron. The address and command signals are not even passing the sstl valid levels when the speed is beyond 200MHz. But below 200MHz it is operating fine. I am planning to operate the SODIMM's at 666Mbps. In simulation we used, SSTL18_IO, SSTL18_I_DCI_O, SSTL18_II_DCI_O buffers but the results are the same. The routed trace length is just less than 5inches. Thanks Samuel ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu