[SI-LIST] Re: : DDR2 Analysis
- From: Benny Luiss <bennyluiss@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 14 Feb 2012 08:56:52 +0530 (IST)
Dear Experts,
Thanks everyone for the clear explanation. I got clarified my doubt.
Regards,
Benny.
________________________________
From: "Beal, Weston" <Weston_Beal@xxxxxxxxxx>
To: Benny Luiss <bennyluiss@xxxxxxxxx>; "si-list@xxxxxxxxxxxxx"
<si-list@xxxxxxxxxxxxx>
Sent: Saturday, 11 February 2012 12:33 AM
Subject: [SI-LIST] Re: : DDR2 Analysis
Benny,
You need to measure setup and hold times of address, command and control
signals relative to the rising edge of the clock. You need to measure setup and
hold times of data signals relative to both the rising and falling edges of the
associated strobe (DQS) signal. There is also a timing relationship between
strobe and clock that you need to verify.
There are simulation tools such as HyperLynx DDR wizard, and others, that can
simulate and measure these timing relationships for you. You still need to
understand the basics of bus timing relationships, but the tool makes the setup
and measurement go much faster.
Regards,
Weston
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Benny Luiss
Sent: Thursday, February 09, 2012 8:47 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: : DDR2 Analysis
Dear Experts,
I have a query on DDR2 analysis. Kindly help to clarify it.
I am using MT47H64M16HR-3IT DDR2- 400 SDRAM device in my design.
I have simulated the clock and data at the frequency of 200 MHz captured at
both raising and falling edge, and Address @ 200MHz captured only at Rising
edge.
But I came to know that, Address and Clock should be simulated with 200MHz on
Raising edge and Data at 200MHz on both the edges.
Please advice which one I need to consider.
Regards,
Benny
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