[SI-LIST] Re: : DDR2 Analysis
- From: Johnson Sebastian <johnson007@xxxxxxxxx>
- To: Benny Luiss <bennyluiss@xxxxxxxxx>
- Date: Fri, 10 Feb 2012 11:30:53 +0530
Hi Benny,
Probe dqs & data on both raising and falling edge
Probe address & command with clock on raising edge.
-Johnson
On Fri, Feb 10, 2012 at 10:17 AM, Benny Luiss <bennyluiss@xxxxxxxxx> wrote:
> Dear Experts,
>
> I have a query on DDR2 analysis. Kindly help to clarify it.
>
> I am using MT47H64M16HR-3IT DDR2- 400 SDRAM device in my design.
>
> I have simulated the clock and data at the frequency of 200 MHz captured
> at both raising and falling edge, and Address @ 200MHz captured only at
> Rising edge.
>
> But I came to know that, Address and Clock should be simulated
> with 200MHz on Raising edge and Data at 200MHz on both the edges.
>
> Please advice which one I need to consider.
>
> Regards,
> Benny
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