[SI-LIST] DDR-1 termination
- From: "Anders Frederiksen" <af@xxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 13 Jul 2005 15:43:20 +0200 (CEST)
> Anders, That 3V I/O will be mighty unhappy if bang on it with a fast DDR
> RAM output. It doesn't take that much to exceed 30% overshoot. If you
> don't want an unpleasant surprise, then I think you had better: simulate,
> get someone else to simulate, find a simulation of a similar channel or
> build a test vehicle.
I'm relying a bit on the Xilinx UG060 that simulates a similar interface. What
worries me is that it's all so nice. Hardly any 'shoots at all!
I know I'd checked a few lines (but unfortunately never documented it) some
months
ago - and didn't find anything alarming.
> If the answer is none of the above, then your
> production design will be the defacto test vehicle.
Sad but true!
> How much will it cost
> your company if the result is unreliable?
Seemingly less than the (possible) delay related to a simulation ? ?cause I
already
pointed that out. But based on the Xilinx ref-design I hope we won't get any
catastrophic surprises... :-O
> Thanks to the cell phone industry, 0201s aren't exclusively vacuum nozzle
> candy anymore. You should be able to find an assembly house that does it
> without grief.
Yeah - there's a lot offering (proved more difficult to find PCB manufacturers
that
would produce 3mil tracks). What we haven't seen yet is failure rates...
Thanks for the input! =)
Best regards,
Anders
> At 10:58 AM 7/13/2005 +0200, Anders Frederiksen wrote:
>>Now I'm scared again. I'm having a design layed out right now with no series
>>resistors. Short (<5cm, probably typically 2-3cm for most banks)
>>transmission lines
>>- but interface towards a Xilinx FPGA that typically is not happy with
>>over/undershoots. Luckily the DDR is only 2.5V - so I think it'll be ok.
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