[SI-LIST] DDR skew
- From: chendla@xxxxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 17 Jan 2003 18:18:46 +0800
Dear all
I am designing a DDR-333 SDRAM application ,and when I calculate
the timing budget ,I find some question.
the DDR controller parameters are like below
DQ input setup time =-0.7ns
DQ input hold time=1.1ns
DQ output setup time(relative to DQS)=0.6ns,symbol is Tsuav
DQ output hold time( relative to DQS)=0.6ns,symbol is Thav
The work frequency of my work is 300MHz,and I don't consider the
board skew and strobe uncertainty, so data read margin is like below
setup analysis:
margin=DVW+700ps=(tHP-tQHS-tDQSQ)/2+700ps
=(6667*0.45-550-450)/2+700ps=1700ps
hold Analysis
margin= 1000ns-1.1ns= -100ps<0 (maybe I should introduce some DQS to DQ
skew?)
and for data write operation,for DQS is center aligned relative to DQ
the setup and hold analysis calculation are here
margin=Tsuav(Data valid to clock transition )
or Thav(Clock transition to data invalid)-tDS(JEDEC DDR spec)
=600-450ns=150ns
from above ,the margin showed is very small,How can I solve this question?
maybe Introducing some DQS to DQ skew?
At last ,Please tell me ,How to calculate the Address/command Bus timing
budget
of DDR sdram ? some applications tell me for address timing margin:
Address/Command output setup time and hold time should be thought as the
amount of the setup
and hold budget consumed by the controller.(not valid window like data
write operation)
but I have doubt.
Thank you very much in advance
best regards
Ralph
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