[SI-LIST] Re: DCD Reduction due to Series Caps on Serial IO
- From: "T.K. Jeon" <tkjeon@xxxxxxxxxxx>
- To: "ah.vinod@xxxxxxxxx" <ah.vinod@xxxxxxxxx>, SI-LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 8 Apr 2013 17:25:55 -0700
I can think about a few things on your DCD.
1. When a termination resistor is put between P and N, you won't have common
mode termination. Therefore, if there is some common mode noise, that will
create common mode reflections at your load and, hence, could affect signal
rise/fall time which will result in DCD.
2. When the signal is probed before/after the caps populated on the dif'l pair,
you see the signals from some distance of the termination, which might have
fraction of reflection signals.
3. If a clock path to drive MUXs inside your serializer is not clean, n:1 MUX
output will inherently have DCD.
4. If RC time constant, which is (Rs+RL)*C_dcblock, of your signal path is too
small, it will cause baseline wander and change the duty cycle.
Best Regards,
TK
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of vinod ah
Sent: Sunday, April 07, 2013 10:22 PM
To: SI-LIST
Subject: [SI-LIST] Re: DCD Reduction due to Series Caps on Serial IO
Hi,
Thanks for pointing out the cap value to be used. I will get it corrected.
But i am measuring DCD with a 4GHz signal i.e. 1010 pattern output from Tx.
I removed the AC-coupling caps and soldered a 100ohm differential
termination across P and N (on the cap pads). Then probe across this
termination to measure DCD using a high impedance differential probe. Did
the same experiment with caps.
Regards
Vinod A H
On Sat, Apr 6, 2013 at 1:54 AM, msmurthy <madiras@xxxxxxxxx> wrote:
> Vinod,
> According to specs for Gen3 operation, AC coupling Cap value shoud be
> 176nF (min)& 265nF (max)
> All platforms that have transmitters supporting 8.0 GT/s must implement
> the 176-265 nF C
> operating at 2.5 or 5.0 GT/s only may implement over a range of 75 to 265
> nF.
>
> We use 220nF to meet the requirements.
>
> I am not sure if this deviation effects DCD measurement but 100nF cap
> value is not suggested when you are doing measurement for PCIe Gen3
> interface.TX value. Platforms
>
> Murthy Madhira
> 503-626-4693(home)
>
>
>
> From: steve weir <weirsi@xxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Friday, April 5, 2013 10:26 AM
> Subject: [SI-LIST] Re: DCD Reduction due to Series Caps on Serial IO
>
> Off-hand I would suspect that your capacitor is closer to the
> transmitter than the receiver and is not transparent, at least not with
> the scope probe in-place. But this depends somewhat on how you test for
> DCD.
>
> Steve.
> On 4/5/2013 4:36 AM, vinod ah wrote:
> > Hi,
> > I am measuring DCD (Duty cycle distortion) on Tx pins of PCIe3 (8Gbps)
> > interface connected to a constant load of 50 Ohms (100 ohms
> differential).
> >
> > What i see is DCD is more when measured before the AC coupling cap,
> rather
> > than after the cap. Looks like AC-coupling cap (100nF) and 50 ohm load is
> > forming a high pass filter.
> >
> > I am unable to understand cap effect on DCD. Any thoughts here?
> >
> > Regards
> > Vinod A H
> >
> >
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