[SI-LIST] Re: Crosstalk between two planes
- From: bala <balaseven@xxxxxxxxx>
- To: Shahbaz Assad <shahbaz_assad@xxxxxxxxxxx>
- Date: Thu, 17 Jun 2010 19:04:00 +0530
Hello,
What will be the SI issue,if we have high speed on outer
layer.?I think, propagation speed on outer layer will be high than inner
layer,which should be good.Don't apply solder mask on high speed traces,if
you think solder mask will cause SI problems.You can use Ansoft HFSS
to check on the impact of solder mask and silk.
On Thu, Jun 17, 2010 at 6:56 PM, Shahbaz Assad <shahbaz_assad@xxxxxxxxxxx>wrote:
>
>
> ****
> *
> *Hi,
>
>
> I think routing the high speed on the external layer leads to signal
> integrity issues due to change is dilecric impedance, silk
> impedance,moisture etc
> What I think is route the high speed in internal layer. Try not to overlap
> the signals means do not route the signals in same x, y but try to do cross
> routing like if you open all the etches of all the layers, no high speed
> signal should hide under other for consecutive layers
>
>
>
> Thanks,
> Shahbaz Assad
>
> System design Engineer - WhizzSystems, Inc.
> _______
> Skypes ID: sassad85 | (+92)-345-66032321
> sassad@xxxxxxxxxxxxxxxx
>
>
>
>
>
>
>
>
>
>
>
> > Date: Thu, 17 Jun 2010 13:58:44 +0530
> > Subject: [SI-LIST] Re: Crosstalk between two planes
> > From: balaseven@xxxxxxxxx
> > To: Jaison.Fernandez@xxxxxxxxxxxx
> > CC: si-list@xxxxxxxxxxxxx
>
> >
> > Jaison,
> > Try to route all address/cmd/ctrl on one layer and data,clock on another
> > layer.Sig#1 and Sig#2 traces should not cross each other.Increase the
> > dielectric space between sig#1 and sig2,which must be higher than Sig-Gnd
> > spacing.Its better if you route the high speed traces on outer layers and
> > route low speed signal on inner layers.
> >
> > On Thu, Jun 17, 2010 at 1:36 PM, Jaison Fernandez (RBEI/EED2) <
> > Jaison.Fernandez@xxxxxxxxxxxx> wrote:
> >
> > > Dear Experts,
> > > I have a layer stack up like as follows:
> > >
> > > 1. Top
> > > 2. Gnd1
> > > 3. Power
> > > 4. Gnd2
> > > 5. Sig1
> > > 6. Sig2
> > > 7. Gnd3
> > > 8. Bottom
> > >
> > >
> > > My board is one which contains ATMEL AT91SAM9M10, 128MB SDRAM (166MHz),
> GPS
> > > Chip solution, High current motor Drivers etc.
> > >
> > > I placed Atmel and SDRAM in bottom layer and routed the SDRAM signals
> in
> > > Sig1 and Sig2 planes.
> > > Could any one tell me the chances crosstalk between sig1 and Sig2
> planes
> > > and possible ways to avoid it.
> > > Due to some tool limitations I can't able to due any POST SI
> > > analysis.(Stack up of Layer1 to Layer 3 is fixed due to some high
> current
> > > applications)
> > >
> > > Regards,
> > > Jaison Fernandez
> > > ------------------------------------------------------------------
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> >
> >
> > --
> > bala
> >
> >
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--
bala
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