Hi SLN,
John's advice is good. A basic model of the connector (such that the FPGA IO
signals are toggled high and low during the test) will give you some coverage,
but to test for open faults with boundary-scan you need something populated in
the connector to drive/sense the signals connected to the FPGA and prove
continuity. The details of how it should be modeled within the software will
depend on how you choose to test it.
I looked into it and our applications engineering group should be responding to
your inquiry this morning; if you don't get the assistance you need, please let
me know and I will follow up.
Bob Deibner
Technical Marketing Engineer
Corelis
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Zelno, John
Sent: Monday, June 13, 2016 8:10 AM
To: lakshminarayanans@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Corelis Boundary Scan Testing tool support
It looks like you'll need to use one of these:
http://www.corelis.com/products-JTAG/Hardware_JTAG_IO_Modules.htm
"The SCANIO family of products use boundary-scan gate arrays to add control and
visibility to connectors, traces, and logic that can not be tested using
traditional boundary-scan techniques."
You could also plug known good memory DIMMs into your DIMM connectors, and use
a Corelis memory test.
-John Zelno
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Lakshmi Narayanan Sowrirajan, ERS-HCLTech
Sent: Sunday, June 12, 2016 10:13 PM
To: si-list@xxxxxxxxxxxxx
Cc: Lakshmi Narayanan Sowrirajan, ERS-HCLTech
Subject: [SI-LIST] Corelis Boundary Scan Testing tool support
Importance: High
Dear Team,
Good morning.
I need support on CORELIS tool, I understand that it is not related to this
list. But am not able to get any support from this tool vendor, that's why I am
writing here.
In my design I have DIMM connectors connected to Xilinx FPGA. I want to model
the connector so that the nets are included in my boundary scan testing.
Similarly I do have PCIe connectors in my design.
So please let me know how can I model connectors with Corelis TPG tool.
Thanks in advance.
Regards
SLN
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