Dear Team,
Good morning.
I need support on CORELIS tool, I understand that it is not related to this
list. But am not able to get any support from this tool vendor, that's why I am
writing here.
In my design I have DIMM connectors connected to Xilinx FPGA. I want to model
the connector so that the nets are included in my boundary scan testing.
Similarly I do have PCIe connectors in my design.
So please let me know how can I model connectors with Corelis TPG tool.
Thanks in advance.
Regards
SLN
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