[SI-LIST] Re: Controlled Impedance Coupon Design
- From: Paul Levin <levinpa@xxxxxxxxxxxxx>
- To: epriest@xxxxxxxxxxxxxxxxxxx
- Date: Thu, 06 Mar 2003 14:16:02 -0800
Dear Ed,
Be careful about such a measurement. Depending on how the end of the
line is configured, you may be measuring an electrical length as much as
one or two percent longer than the actual metal. "End effect" is the term
for this. You can also see this effect if you vary the width of the trace;
that will effectively lengthen it.
Regards,
Paul
__________________
Ed Priest wrote:
> A neat trick I've used to measure the propagation delay. Instead of
> trying to pick off the delay from a TDR (you always have some accuracy
> issues with picking the starting and ending points) is to build a test
> stub.
>
> |
> |
> |
> C ---------------------------------- C
>
> Look at S21 between the two connectors and the frequency distance
> between the minimums will be the 1/2 wavelength. It's an easy relative
> measurement to pick off the curve. Even without a VNA - a simple
> frequency sweep provides very accurate results.
>
> Ed
>
> -----Original Message-----
> From: Ken Willis [mailto:kwillis@xxxxxxxxxxx]=20
> Sent: Thursday, March 06, 2003 8:50 AM
> To: brian.butler@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Controlled Impedance Coupon Design
>
>
> H Brian
>
> Besides impedance, another critical aspect is the prop delay
> characteristics per layer. This gets really important whey you
> are trying to control skew between clock and data lines to 10's
> of picoseconds. The impedance coupons could help a lot if, instead
> of all the test lines on a layer just being a standard 6" length,
> there was an additional line that was a different known length
> on each layer. For example if there were an additional test line
> 4 inches long, then the engineer could figure out with a TDR the prop
> delay/inch for the various layers, and could more accurately design
> the skew offsets into the layout. I think this will be more and more
> important as we go along to higher speeds. This idea has been proposed
> on the SI-list more than once. I'm sure people are doing this on their
> own today, as I have done in the past.
>
> Ken=3D20
>
> -----Original Message-----
> From: Brian Butler [mailto:brian.butler@xxxxxxxxxxxxxxx]=3D20
> Sent: Tuesday, March 04, 2003 11:28 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Controlled Impedance Coupon Design
>
> To All:
>
> The IPC task group which is rewriting the IPC-2141 Controlled Impedance
> =3D
> Circuit
> Boards and High Speed Logic Design is looking into the need of rewriting
> =3D
> the
> Controlled Impedance Coupon Design Rules (Section 4.7 of current =3D
> document) and
> would welcome your input on the following issues concerning controlled
> impedance coupon design. Please feel free to comment on any or all of =
> =3D
> the below
> listed points.
>
> Potential Topics for Controlled Impedance Design Rules
>
> 1) Terminate or un-terminated traces?
> 2) Test points are plated thru holes?
> 3) Size of Drilled Hole?
> 4) Size of pad?
> 5) Single-ended pitch between signal and ground?
> 6) Differential pitch and pattern?
> 7) Differential pattern (no ground reference, one ground reference,
> =3D
> two
> ground references)?
> 8) Width of coupon?
> 9) Length of test trace?
> 10) Use of thieving?
> 11) Need for consistent orientation of probe pads to eliminate the =
> =3D
> need for
> test operators to rotate the probe (repetitive stress)?
> 12) Bends in trace or no allowed bends?
> 13) Minimum spacing from one test structure to the next?
> 14) Type of nomenclature and clearance specifications?
> 15) Tie all ground/power planes together on coupon?
> 16) Ideal location of coupon(s) on panel?
> 17) Square lands to identify grounds/power reference points?
> 18) Other issues?
>
>
>
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--
Paul Levin
Senior Principal Engineer
Xyratex Storage Systems
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