[SI-LIST] Re: Component Placement Doubt
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Lakshmi Narayanan Sowrirajan, TLS-Chennai" <lakshminarayanans@xxxxxx>
- Date: Fri, 04 Sep 2009 06:10:02 -0700
Potentially it could cause you considerable problems. This all depends
on how you have managed your noise currents. There is enough plane
thickness that field penetration is not an issue. But transverse noise
currents in the planes is a potential issue. Plane cavities form
transmission lines. Currents flowing through them result voltage
potentials between different points. To the extent any of that voltage
appears across nodes that are part of your clock generator circuit it
can disturb it. The other issue that could get you is leakage from your
magnetics into passives on the same side of the PCB.
Steve.
Lakshmi Narayanan Sowrirajan, TLS-Chennai wrote:
> Hi All,
> Good day to all.
> I have a doubt in the component placement as described below,
> please help me in this.
>
> My PCB is 24 layers with 8 layers of GND and the board
> thickness is nearly 2.8mm. I have placed a switching regulator operating at
> 1100KHz (LT3502) with 1.8V output and load current of less than 900mA on TOP
> layer and a Differential clock synthesizer (Si5338A) at the BOTTOM layer
> operating at 2.5V. I don't have any through via in this area.
>
> Please let me know how this placement is going to affect the
> Jitter performance and the quality of clock at the output of the Si5338A. I
> am really confused in this. Please give your concerns / suggestions at the
> earliest as I have my release very near.
>
> Thanks in advance for your time and clarifications.
>
>
> Regards
> Lakshminarayanan.S
>
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