[SI-LIST] Re: Comparing layers on two artworks
- From: "Red Wire" <redwire@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 16 Apr 2008 15:57:59 -0500
It seems as though you want to implicitly declare critical signals but don't
want to bother constraining them.
As a full-service SI and PCB layout house I only accept critical signals
with constraints -- not passed to me by voicemail. I will often apply
additional constraints my customer's missed but I won't take the heat
because of a lazy engineer or 'accelerated' design cycle.
The tool (Allegro) is designed to use constraints and you can always verify
that none of your constraints were changed.
And you may not have the same vantage point as those of use who actually
design boards instead of schematics. Why should you care if your 'critical'
was moved if it meets the design requirements?
I would suggest applying constraints instead of the 20 year old method of
'comparing' Gerber files. You can always print the traces out on film and
hold them up to the light if you find that more intuitive.
My .02.
Bill Dempsey
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Nima Lotfi
> Sent: Wednesday, April 16, 2008 1:03 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Comparing layers on two artworks
>
>
> I'm looking for input on a tool for comparing artwork. I've done a
> quick search of the archives and haven't seen anyone discuss this
> topic.
>
> Whenever I re-spin a board it involves changes to perhaps about 10% of
> the nets (a typical board would have 5000 to 8000 nets), however,
> there is a potential that tools or layout person that is running tools
> may make unintended changes to traces that should not have been
> touched.
> This is has become more of problem as layout resources are outsourced,
> and they are often not collocated with hardware designer. =20
>
> Since most signals of importance are often constrained, changes are
> most likely insignificant or significant changes get caught by a
> design rule check. However, if a constraint on a critical signal is
> missed than there can be potential exposure and risk to the design
> cycle.
> I'd like
> to minimize this risk, and that brings me to my question
>
> I am wondering if any one is aware of any tools that can compare and
> report changes on different artworks layer by layer.
>
> The design tools we use are Cadence Allegro, and the output we
> generate is ODB+. =20
>
>
> Best Regards,
> =20
> ______________________=20
> Nima Lotfi, P. Eng=20
> Hardware Design Engineer=20
> Nortel
> Calgary, Alberta, Canada=20
>
> 758-7786 ESN=20
> (403) 769-7786 Direct=20
> (403) 769-7176 Fax=20
> LNima@xxxxxxxxxx=20
>
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