Hi I suppose I don't fully understand the term "source-synchronous". I have been thinking it referes to all kinds of buses which operate off a non-central clock, e.g: The PowePC interface to its L2 cache, which is clocked by a "L2 Clock" driven by the PowerPC chip. Regards abe riazi wrote: > Itzhak Hirshtal Wrote: > > The answer to your question depends on the chip vendor's definition! I'm > accustomed to a definition which is in respect to the strobe <<output>> pin, > but > Mr. Riazi's definition for a source-synchronous design seems to be in respect > to > the strobe <<input>> pin, that's why he has both Tco_data and Tco_strobe (see > his answers to me). I also understand that he refers to a design in which the > strobe signal is used to capture the data on the <<opposite edge>> than the > edge > on which the data is transmitted. <<I>> refered to a source-synchronous bus > which samples the data at the receiver on the same dege as the one used to > transmit the data. > > Hi Itzhak: > > Please clarify: > > "he refers to a design in which the > strobe signal is used to capture the data on the <<opposite edge>> than the > edge > on which the data is transmitted. <<I>> refered to a source-synchronous bus > which samples the data at the receiver on the same dege as the one used to > transmit the data" > > The Source synchronous computer front-side bus (FSB / GTL) designs I have > simulated, > have included a chipset (example: CMIC-LE ) plus two or more processors > (example: Pentium IV). > These buses have operated at 133 or 100 MHz. When the chipset drives, it > first transmits data > signals and a short while later the associated strobes. To ensure proper > functioning of such source > synchronous buses, the strobe must be timely transmitted to satisfy the setup > and hold requirements > of the receiver latch. The ideal offset between data and strobe is usually > 90 degrees assuming > 50% duty cycle. > > All agents on FSB data interface are bi-directional; therefore, a complete > GTL simulation necessitates > not only considering the case of chipset driving but also when a Middle or > the End processor drives. > > Common clock timing analysis is required because of data to bus clock > relationships; whereas, the > data to strobe relation dictates source synchronous setup and hold margin > computations. When > generating/interpreting a source synchronous timing spreadsheets, it is > important to take into account > that a group of data signals (for example 16 data bits) can share the same > strobes. > > Thank you, > > Abe Riazi > ServerWorks > > ------------------------------------------------------------------ > To unsubscribe from si-list: > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field > > or to administer your membership from a web page, go to: > //www.freelists.org/webpage/si-list > > For help: > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field > > List archives are viewable at: > //www.freelists.org/archives/si-list > or at our remote archives: > http://groups.yahoo.com/group/si-list/messages > Old (prior to June 6, 2001) list archives are viewable at: > http://www.qsl.net/wb6tpu -- Itzhak Hirshtal Elta Electronics POB 330 Ashdod Israel 77102 Tel : 972-8-8572841 Mobile: 972-64-238631 Fax : 972-8-8572978 email: hirshtal@xxxxxxxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu