[SI-LIST] Clock net correlation_current mode current steeling
- From: "Sogo Hsu" <sghsu55@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 12 Nov 2002 02:23:12 -0000
Hi Gurus,
I have a question regarding clock generator net topology. The net
consists of clock generator and CPU/MCH. The guideline recommends add
a resistor nearby clock generator due to the circuit is current mode
current steeling. Simulation depicts the signal quality will be
better if I remove the resistor close CPU/MCH. Especially, the
waveform is more flat than the design follows guideline. However,
measurement reflects the inverse trend. I don=A1=A6t know the reason.
Theoretically, the resistor placed close receiving end will reduce
reflection and ring. Simulation also depicts the same expectation.
But the guideline and measurement presented this idea is wrong. Why
the simulator (SPECCTRAQuest/SPEED) can=A1=A6t show the correct behavior
in this issue? Thank you in advance.
Best regards,
Sogo Hsu
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