[SI-LIST] Re: Circuit for differential to single end conversion

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: vats123@xxxxxxxxx,si-list@xxxxxxxxxxxxx
  • Date: Wed, 02 Aug 2006 08:28:10 -0700

Srivatsan,  you can either rework the diff stage that you have or add 
stages as needed.  Is your limited swing due to the way you are 
biasing your output stage, or are you running out of GBW?  If you 
have enough GBW the circuit s/b a text book logic design.  At 250nm 
GBW may be the problem.

Steve.
At 07:43 AM 8/2/2006, Srivats Partha wrote:
>Hello gurus
>I have differential signals(2 Gbps) coming from Xilinx Rocket IO to 
>the chip. I have designed a front end differential receiver that 
>receives this differential signal.
>The problem I have is the output at the end of my receiver swings 
>from 1.8 to 2.5 and the next stage circuitary that I have is single 
>ended. It requires full swing CMOS inputs (0-2.5). How do i convert 
>this differential output at the end of my receiver (1.8-2.5) V to 
>single end (0-2.5). The data rate is 2.0 Gbps. Iam using TSMC 0.25d process.
>Thanks
>  Regards
>Srivatsan.
>
>
>--
>P.Srivatsan
>Graduate Student
>ECE Dept,North Carolina State University
>http://www4.ncsu.edu/~spartha2/
>--
>I have no special talents. I am only passionately curious. AE
>
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