[SI-LIST] Re: Circle bus topology
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: David.Carney@xxxxxxxxxx
- Date: Thu, 26 Jul 2007 11:32:26 -0400
David
We used to design memory address topologies that way over 10 years ago.
We called it a loop topology. It does work well in some instances, as
long as you can keep the edge rate and signaling rate below the
resonance frequency of the loop. As Ron Miller discusses, in microwave
design, this is known as a circular resonator.
The largest reason why it is not often used in digital design, is one of
testability. A straight loop is untestable. It is, however, possible
to test a loop with two series resistors.
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
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(401) 284-1827 Business
(401) 284-1840 Fax
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David Carney (Neenah) wrote:
> Has anyone ever experimented with a circle bus topology. The basic
> concept would be a bus with several devices attached. They would be
> routed in a daisy chain topology, and then the two ends of the daisy
> chain would be connected together. The PCB routing would look like a
> circle or a loop for each net on the bus. Pointers to references such
> as papers or application notes would be greatly appreciated. I'm
> particularly interested in signal integrity and EMC implications of this
> topology.
>
> Thanks.
>
>
> ----------
> David Carney
> Senior Hardware Engineer
> Plexus Corp.
> Phone - 920-751-5646
>
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