[SI-LIST] Re: Check LPDDR2 CK-DQS timing
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: zlqin80@xxxxxxxxxxx
- Date: Tue, 18 Sep 2012 09:24:11 +0200
Yes,
all DRAM specs just define what need to be applied at the DRAM inputs.
Controller are not commodity (unfortionally ;-) ).
Calculating the timing budget is therefore part of the design process
for each design.
I guess you mentioned this already (but somehow the formatting was lost,
so your e-mail was difficult to read):
You need to consider all uncertainties: Contoller output uncertainty,
Routing lenght mismatch and Channel introduced jitter on clock and DQS
(not sure if I forgot anything). Add all of this together and you should
be still below the allowed skew at the DRAM inputs...
Hemrann
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Am 18.09.2012 08:57, schrieb qinzuli:
> Hi, I'm going through LPDDR2 spec for CK-DQS timing definition on DRAM
> side. The spec has defined tDQSS/tDSS/tDSH parameter to represent tDQSS:
> the min./max. latching time from clock rising edge to the first strobe
> rising edge tDSS: the min. setup time margin required from strobe
> falling edge to corresponding clock rising edge tDSH: the min. hold
> time margin required from strobe falling edge to corresponding clock rising
> edge. For LPDDR2 there is no write leveling feature. I know {tDQSSmin,
> tDSH} and {tDQSSmax, tDSS} should be checked pairly. According to
> LPDDR2 spec, tDQSSmin = -0.25 * tCK(per) tDQSSmax = 0.25 *
> tCK(per) tDSS = 0.2 * tCK(per) tDSH =
> 0.2 * tCK(per) tDQSSmin and tDQSSmax could be regarded as Worst Case timing
> relationship between CK and DQS rising edge, right? For 533 MHz clock
> frequency, there is only 0.05 * tCK(per) = 93.75 ps skew margin I
> checked some LPDDR2 de
> sign IP (Driver side) spec which give total transmitter uncertainty from DQS
> to CK is 130 ps @533MHz. How should user to consider the Driver side skew
> while checking CK-DQS timing? Seems LPDDR2 spec only focus on DRAM side. If
> the max. transmitter skew is about 130ps, also adding to interconnect
> skew(Package/PCB/RDL skew and mismatch), then totally all the Tx/Interconnect
> Skew will acceed the allowed skew margin of DRAM. Is my understanding right?
> Thanks for your correction. Best regards,Ben.> Date: Tue, 18 Sep 2012
> 07:46:52 +0200
>> From: Hermann.Ruckerbauer@xxxxxxxxxxxxx
>> To: fbhatti@xxxxxxxxxxxxxxxx
>> CC: venkatarao.S@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: Daisy chain topology for DDR2 addressing signals?
>>
>> Hi
>> having 5 DRAMs in a row for DDR2 (unterminated at the end ?) is very
>> risky and most likely not to work.
>> on the DIMM designs there is often not a full T implemented, but with e.
>> g. 2 DRAMs in a row.
>> Is this done Desing with a Register for CA ?
>>
>> Take a look to JEDEC R/C F or G (both registered) and use the topology
>> and length matching requrement from this Design.
>>
>> Hermann
>>
>> Our next Events:
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>> "Open the Black Box of Memory"
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>> www.EyeKnowHow.de
>> Hermann.Ruckerbauer@xxxxxxxxxxxxx
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>> 94554 Moos
>> Tel.: +49 (0)9938 / 902 083
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>> Am 18.09.2012 07:34, schrieb Farooq:
>>> Hi Venkat
>>> You would be better off using a T-topology for address/control with
>>> termination at each brach end
>>> It would be easier to length match the whole interface
>>>
>>> Regards
>>> Farooq Bhatti
>>>
>>> Sent from my iPhone
>>>
>>> On Sep 17, 2012, at 10:19 PM, "Venkatarao.s" <venkatarao.S@xxxxxxxxxx>
>>> wrote:
>>>
>>>> Hi all,
>>>>
>>>>
>>>> For 72 -bit DDR2 interface, we are using 5 DDR2 devices each having 16-bit
>>>> data width .All five DDR2 address signals are shared, So can I use Daisy
>>>> chain topology for DDR2 addressing signals?
>>>>
>>>>
>>>>
>>>> Please suggest topology.
>>>>
>>>>
>>>>
>>>> Regards,
>>>>
>>>> Venkat
>>>>
>>>>
>>>>
>>>>
>>>>
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