[SI-LIST] Re: Capacitors Behavior in None Equipotential Surface
- From: Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
- To: krhoads@xxxxxxxxxxxxxx
- Date: Fri, 28 Nov 2014 14:10:04 -0500
Hi Kevin;
Thanks for your comments. In ASIC design we generally add thousands of
small decaps
(perhaps 10s of thousands is more accurate). To model the effect of
capacitance we assume
they all connected to one node (between power and ground) and then we do
transient simulation
to understand the mitigation effect of noise. I was looking for reasonable
numerical accuracy.
I was always wondered if assumption of equipotential or none eqipotential
has any significant
effect in amount/number of decaps that I add to silicon (Hope I am making
sense here).
You mentioning usually simple corrections to the equipotential solution
will suffice. I am sort of
looking for some fudge factor from engineering point of view (i.e less math
and complication :-)).
Can it be like add/subtract 5 or 10 per percent to equipotential case and
be done with? I understand
that an easy answer may not be possible but I was sort of thinking along
those lines. Hope this helps..
thanks.
Regards;
Don Pakbaz
From: "Kevin G. Rhoads" <krhoads@xxxxxxxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: 11/28/2014 12:58 PM
Subject: [SI-LIST] Re: Capacitors Behavior in None Equipotential Surface
Sent by: si-list-bounce@xxxxxxxxxxxxx
In one dimension, you would be looking at an RC or RLC transmission
line. When a conductor is not equipotential, usually that can be
modelled as impedance - resistance, inductance or both together.
In two dimensions, somewhat more complicated, but still separation of
variables for the two space and one time or frequency in your model.
Circuit models of 1D RC transmission lines exist in electrochemistry,
e.g., Warburg.
How detailed do your numerics need to be? Usually, simple corrections
to the equipotential solution will suffice, but not always.
Sincerely
Kevin G. Rhoads, Ph.D.
On 11/28/2014 12:24 PM, Faraydon Pakbaz wrote:
>
> Dear Experts;
>
> We know that theoritically capacitors in parallel add in equipotential
> surface. What about
> None equipotential surface? Is there any good way to approximate the
> capacitors behavior
> in None Equipotential surface? This question arises from considering the
> total capacitor required
> at chip level. Even though assumption often made that Chip/Silicon level
is
> equipotential, we
> know that in reality is not due to various high frequncy cores running at
> silicon. Thanks in advance
> for comments and guidance.
>
> Regards;
>
> Don Pakbaz
>
>
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