[SI-LIST] Re: Capacitors Behavior in None Equipotential Surface
- From: "Kevin G. Rhoads" <krhoads@xxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 28 Nov 2014 12:56:32 -0500
In one dimension, you would be looking at an RC or RLC transmission
line. When a conductor is not equipotential, usually that can be
modelled as impedance - resistance, inductance or both together.
In two dimensions, somewhat more complicated, but still separation of
variables for the two space and one time or frequency in your model.
Circuit models of 1D RC transmission lines exist in electrochemistry,
e.g., Warburg.
How detailed do your numerics need to be? Usually, simple corrections
to the equipotential solution will suffice, but not always.
Sincerely
Kevin G. Rhoads, Ph.D.
On 11/28/2014 12:24 PM, Faraydon Pakbaz wrote:
>
> Dear Experts;
>
> We know that theoritically capacitors in parallel add in equipotential
> surface. What about
> None equipotential surface? Is there any good way to approximate the
> capacitors behavior
> in None Equipotential surface? This question arises from considering the
> total capacitor required
> at chip level. Even though assumption often made that Chip/Silicon level is
> equipotential, we
> know that in reality is not due to various high frequncy cores running at
> silicon. Thanks in advance
> for comments and guidance.
>
> Regards;
>
> Don Pakbaz
>
>
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