Priya, you should develop an inductance budget and ESR target. Then
based on your stack-up and the IC package work from there. There is no
special correspondence between power pin count and capacitors.
Depending on the stack-up and geometry too many capacitors can hurt
performance on top of adding to cost. The "puddle" concept works well
in these sorts of situations. You can pull papers on that from my web
site, or X2Y's web site, and I believe if you dig you may be able to
find it on DuPont's web site as well. The idea is that when inductance
is dictated by Z axis, you can use a lot fewer capacitors if they attach
to a thin cavity near their mounting surface. This keeps the ESL down
and the low capacitor count makes it easier to realize an appropriate ESR.
Steve.
On 7/6/2015 10:24 PM, Priya D wrote:
Steve,
Thank you for the explanation. Also I have a doubt regarding the
number of decaps we can place in the other side of the DUT (below the
power pins). If suppose there are 10 power pins in DUT should I place
only less than 10 decaps below DUT. How to determine the maximum
capacitance loading.
Regards,
Priya
On Jul 6, 2015 11:01 PM, "steve weir" <weirsi@xxxxxxxxxx
<mailto:weirsi@xxxxxxxxxx>> wrote:
It depends. Generally EDA software such as Sigrity generates an
acceptable approach. If the interconnect inductance dominates
impedance
to the UUT, then the distributed capacitor values do little to flatten
the impedance seen by the UUT. The UUT sees the PDN as inductive down
typically to a few MHz. Using different values of capacitors will
have
an impact on resonances at the board level. Distributing the
capacitors
by value around a uniform power cavity will tend to minimize the
resonant peaks. Beware assumptions as there are exceptions.
Steve
On 7/6/2015 10:09 AM, Priya D wrote:
> Hi experts,
> I need a clarification regarding capacitor placement order in PCB.
> Generally the capacitor value should be in decreasing order
from the
> source towards sink (tester region - POGO to DUT).
> When I optimize the capacitor values using EDA tool to the lower
power
> impedance in the frequency range of DC to 50MHz, cap values are
optimized
> in such a way that the values scatter randomly in the PCB
instead of lower
> value decap at DUT, mid value cap near DUT and bulk cap at POGO
region.
>
> Will this random optimization have any impact??
>
>
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