+SI-LIST
Hi Arpadï¼
Thanks , I forgot to cc to si-list, re-send and add si-list in the loop.
Regards
Robbie
arpad.muranyi@xxxxxxxxxxx <arpad.muranyi@xxxxxxxxxxx> äº2024å¹´4æ9æ¥å¨äº
00:52åéï¼
Lui,
I donât think you can use the [External Circuit] like that (in parallel
with a [Model]).
But you might be able to do it with the [Interconnect Model] and related
keywords, though. I didnât try it yet, so I canât
say for sure, and I canât tell you how to do it exactly, but while these
keywords were primarily invented for package
modeling, you can use them for âdecoupling modelsâ between power and
ground. Since these keywords allow you to
make connections at pin, at pad, and at buffer terminal, you may be able
to connect something between the bufferâs
power and ground terminals (PU_ref, PD_ref) and model your predriver and
core noises that way.
Let me know if you need more hints along these lines.
I hope this will give you some ideas on how to do itâ¦
Thanks,
Arpad
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*From:* Luping Liu <liewluping@xxxxxxxxx>
*Sent:* Sunday, April 7, 2024 6:34 AM
*To:* Muranyi, Arpad (DI SW EBS PST AV) <arpad.muranyi@xxxxxxxxxxx>
*Subject:* Re: Can we use IBIS model generate SSN current?
Hi Arpad:
Thanks , your reply is very helpful.
Indeed, I have both IBIS and HSPICE models on hand, and also the pwl
current file from the vendor too.
What I am thinking is how to make things simple, the best way is one
model for all simulations.
My first idea is , add a 'compensate current table' parallel
connected with the power pin of IBIS modelï¼ use [External Circuit] or
similar key wordsï¼, this current should include the pre-driver and core
circuits (VDD/VDDQ should have a separate table), the table should
correlate with the edge of the output buffer.
Do you have any suggestions for this idea?
Thanks and regards
Robbie
Msg: #3 in digest
From: "arpad.muranyi @ siemens . com" <dmarc-noreply@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: Can we use IBIS model generate SSN current?
Date: Wed, 3 Apr 2024 16:46:28 +0000
Robbie,
That all depends on how the model maker creates his/her model. SPICEthe best method is...
models are not necessarily better because
they are SPICE models...
But yes, the modeling language may have a say in what you can or cannot
model with the language. The various
modeling languages were invented to address specific needs, usually with a
tradeoff between speed and accuracy.
In some cases, "better" means more accuracy, but in other cases it might
mean orders of magnitudes faster.
To answer your question, IBIS models can be written with "power aware"
features which account for the currents
going through the power and ground pins of the device. However, if you do
this with the [Model] keyword, you
can only account for the currents for the output stage of the buffer.
Pre-driver or core currents are not included
in such buffer models. On the other hand, if you use the more advanced
capabilities in IBIS, the [External Model]
or [External Circuit] keywords with the associated advanced modeling
languages, Verilog-A or VHDL-AMS, you can
make your model perform miracles if you like... ð
IBIS-AMI models are somewhat different. They are basically based on
signal processing algorithms, using an
impulse response of the channel. This impulse response is a snapshot of
the channel, like a single frame from a
long video. The signal processing algorithms in the AMI model takes this
"still picture" and tries to make a movie
out of it, however, this movie may not end up with the same details that
were in the original video...
IBIS-AMI models rely on the assumption that the channel is LTI (linear and
time invariant). Time invariance means
that the power supply voltages do not change during the time of the
"simulation". If you want to simulate the
effects of power fluctuations, you need to ask your model vendor to make
models for you which are made for that
purpose. IBIS-AMI models are not necessarily the best choice for that
purpose.
I hope this gave you some insight into power aware simulations and
modeling...
Thanks,
Arpad
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