To both your questions, Correct and correct.
On Sun, Apr 7, 2024, 7:17â¯AM Luping Liu <liewluping@xxxxxxxxx> wrote:
Hi Benjaminï¼
Thanks for your sharingï¼just want to confirm that you are connecting
the IBIS power pin with the 'VDDQ PDN ' in the *Figure 15. DDR4-2400
READ simulation setup to assess VDDQ compliance ?*
Then based on the correlation Cdie result between simulation and
vendor updatedï¼ we can conclude that the IBIS model here can model the
current draw from the PDN ï¼
Benjamin Dannan <ben@xxxxxxxxxxxxxxxxxxxxxxx> äº2024å¹´4æ3æ¥å¨ä¸
18:44åéï¼
Hello Robbie,
Yes you can use an IBIS model to do DDR PI+SI co-simulation. I have done
this multiple times. The caveat is the IBIS model must be power aware (IBIS
version 5 or later) and have necessary I-V curves.
In fact, some IP vendors will not give you a SPICE model and tell you to
use their IBIS model to do any power integrity or PI+SI analysis.
As an example you can reference an article I co-wrote with a colleague on
the SIJ at the link below. In this example we show how to use the IBIS
model do explore the PDN noise on the PKG+die to assess AC+DC voltage
compliance to the vendor's spec. In this example initially we were given
the incorrect die model Cdie and we had to use this to prove what the
correct Cdie needed to be.
https://www.signalintegrityjournal.com/articles/3386-what-is-enough-vddq-package-power-integrity-analysis-with-a-ddr4-phy
If you have any questions feel free to reach out to ask.
V/r
Ben
On Wed, Apr 3, 2024, 6:23â¯AM Luping Liu <liewluping@xxxxxxxxx> wrote:
Hi Expertsï¼
When we do DDR SI+PI co-simulationï¼ the best method is use spice model
to generate the VDDQ current .
But most of time , we only have IBIS/AMI model on hand , my question
is
, is IBIS can be, or will be used to mimic the current draw from the VDDQ
PDN?
I see many application are focus on the PDN noise impact to IO jitter
with IBIS model , but rarely see the reverse operation , does any
reasearch
on this area?
Thanks and Regards,
Robbie
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