Yannick, I think what you have done is reasonable. From a sinusoidal steady state standpoint, maximum power is delivered to the load when RS=R0=RL. Under this condition, ideally no reflections occur, and VL=VS/2. It appears as though you have achieved your desired attenuation by setting RL slightly greater than R0. (RS-total source output resistance including term, R0-characteristic impedance, RL-total load resistance including term.) A consideration that may be an issue is the fact that you will deliver more power to the load including RL. This may not be the desired effect. In order to increase R, you could place an R divider at the receiver, using larger values for resistance to get your attenuation without consuming as much power. This approach may be a little bit unorthodox as well. You could also reduce your signal swing at the driver with an r divider. You would have to increase your series term resistance and then tie its output with a resistance to ground that would have a parallel combination of R0 for matching. This way the resistances are larger and may consume less power. Power is complicated at driver due to the reflections. You can get an idea of average power by inserting the appropriate I,V macro and examining output. I have never tried such things, and there may be a much more elegant solution, but if you run these ideas in spice, you should be able to make them work. You could also try them out with some careful soldering to your prototype. Good luck, James J. -----Original Message----- From: Yannick Gagnon [mailto:ygagnon@xxxxxxxxxxxxx] Sent: Tuesday, January 29, 2002 10:34 AM To: SI-LIST (E-mail) Subject: [SI-LIST] CLK Input not 3.3V tolerant Hello All, I have a clock signal that is generated by a clock buffer (pwr supply = 3.3V) and is sent to a device that is not 3.3V tolerant (pwr supply = 2.5V). The series termination is there to reduce the ringing and I have put a resistor R tide to the ground just before the input pin in order to reduce the signal to 2.5V. |>---/\/\/-----------------------------|> | [R] | | GND I did simulation in HSpice and it does what I want, the signal is reduced to 2.5V and the signal is clean, but from more experienced designers this practice is unusual. I was wondering if anybody had ever done this or something similiar. I would appreciate your feedbacks. Best regards, Yannick ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu