[SI-LIST] Re: Board layout issue

  • From: cadpro2k@xxxxxxxxxx
  • To: <scott@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Tue, 16 Jul 2002 08:19:42 -0800

Great catch Scott. I was thinking the same thing, since we saw a "demo" 
of what Synchron has, and recognized the name. Keep 'em honest. :)


---------Included Message----------
>      Date: Mon, 15 Jul 2002 18:45:15 -0700
>      From: "Scott McMorrow" <scott@xxxxxxxxxxxxx>
>      Reply-To: <scott@xxxxxxxxxxxxx>
>      To: <mmanginella@xxxxxxx>
>      Cc: <ajmani@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
>      Subject: [SI-LIST] Re: Board layout issue
>      
>      
>      Mike,
>      
>      Why didn't you just go ahead and say that you are with Syncron 
>      Technologies?  Your posting is a bit deceptive. In your posting 
you 
>      speak as if you are a helpful third person and not an employee of 
Syncron. 
>      
>      This group has never had a problem with vendors mentioning that 
they 
>      have a product which might take care of a particular engineering 
issue 
>      that is being discussed.
>      
>      By the way, the layer stackup optimizer does not seem to be 
mentioned on 
>      your web page.
>      
>      regards,
>      
>      scott
>      
>      -- 
>      Scott McMorrow
>      Teraspeed Consulting Group LLC
>      2926 SE Yamhill St.
>      Portland, OR 97214
>      (503) 239-5536
>      http://www.teraspeed.com
>      
>      
>      Mike Manginella wrote:
>      
>      >There is a company, Syncron Technologies 
(www.syncrontechnologies.com) that
>      >has a layer stack up optimizer.  The interesting thing about it 
is you can
>      >enter constraints for line and layer impedances as well as other 
material
>      >properties and get a good idea of the number of board layers to 
use.  It is
>      >constraint driven design for SI.
>      >
>      >
>      >Thanks
>      >Mike Manginella
>      >
>      >----- Original Message -----
>      >From: "Ravinder Ajmani" <ajmani@xxxxxxxxxx>
>      >To: <si-list@xxxxxxxxxxxxx>
>      >Sent: Friday, July 12, 2002 3:48 PM
>      >Subject: [SI-LIST] Board layout issue
>      >
>      >
>      >  
>      >
>      >>Hi Layout Gurus,
>      >>Is there a quick and dirty method to determine if a circuit can 
be routed
>      >>on an FR4 board of certain dimension, by taking in to account 
the
>      >>    
>      >>
>      >available
>      >  
>      >
>      >>card area and cumulative area of all components.  The card will 
be about
>      >>0.8mm thick with six layers (four signal and two power).  I do 
not have
>      >>    
>      >>
>      >the
>      >  
>      >
>      >>option to use microvia or any other exotic technology.
>      >>
>      >>Your input will be very much appreciated.
>      >>
>      >>Regards, Ravinder
>      >>PCB Development and Design Department
>      >>IBM Corporation
>      >>Email: ajmani@xxxxxxxxxx
>      >>
>      >>    
>      >>
>      
>***************************************************************************
>      >  
>      >
>      >>Always do right.  This will gratify some people and astonish 
the rest.
>      >>.... Mark Twain
>      >>
>      >>
>      >>
>      
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>      >  
>      >
>      >
>      >  
>      >
>      
>      -- 
>      Scott McMorrow
>      Teraspeed Consulting Group LLC
>      2926 SE Yamhill St.
>      Portland, OR 97214
>      (503) 239-5536
>      http://www.teraspeed.com
>      
>      
>      
>      
>      
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>      
>      
---------End of Included Message----------
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