[SI-LIST] Re: Bit pattern for high speed serial link simulation
- From: "Pratt, Gary" <gary_pratt@xxxxxxxxxx>
- To: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>, "Scott McMorrow" <scott@xxxxxxxxxxxxx>
- Date: Tue, 29 Nov 2005 19:02:39 -0500
Its on the same order of magnitude as a tool that will simulate the
encrypted transistor-level models provided by FPGA vendor. Same order
of magnitude as the NRE involved with a couple of prototype board spins
as well. But I agree, definitely not something for a hobby shop. =20
-----Original Message-----
From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=20
Sent: Tuesday, November 29, 2005 4:55 PM
To: Pratt, Gary; Scott McMorrow
Cc: Perry Qu; si-list
Subject: RE: [SI-LIST] Re: Bit pattern for high speed serial link
simulation
So you are suggesting a designer on a FPGA budget to get your AMS tools.
How does the pricing of AMS compares with a $3K SPICE license ?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Pratt, Gary
Sent: Tuesday, November 29, 2005 2:29 PM
To: Scott McMorrow
Cc: Perry Qu; si-list
Subject: [SI-LIST] Re: Bit pattern for high speed serial link simulation
Good point Scott. This is another reason to avoid frequency-based
analysis techniques which can't model crosstalk from non-linear drivers.
=20
But, the AMS simulator in question can certainly handle coupled package
models for signal and power connections. In fact, the s-parameter
DesignCon paper I mentioned focuses on using a 200+ pin s-parameter
package model for SSN application. Such a model could certainly be
incorporated into a channel analysis (assuming we could such a model
from the silicon vendor). We could even incorporate a model of the PCB
power planes as well, although from what I understand from measurements
made by the primary author of the DesignCon paper (an SSN expert at an
FPGA company), the PCB power distribution is not a significant factor at
the edge rates involved with GBs speeds. So, that would probably be a
little over-kill.
=20
But, your point is well taken. The simulation would certainly be
overstated without fully coupled power/signal package models. Is there
*any* way to accurately predict the right results without access to
detailed package models (other than building a million prototypes and
hoping one of them includes all the worst-case parts :) )?
=20
Gary
=20
=20
=20
________________________________
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Tuesday, November 29, 2005 3:25 PM
To: Pratt, Gary
Cc: Perry Qu; si-list
Subject: Re: [SI-LIST] Re: Bit pattern for high speed serial link
simulation
Gary
Although the V2 is straightforward from a driver/receiver technology
standpoint, differential drivers and receivers do not exist in a ideal
environment, especially those that reside on FPGAs. Without fully
coupled package models and full power delivery models, any attempt to
simulate this particular Serdes will result in an overestimate of it's
capabilities. Actual performance is much worse than simulated
performance.
I don't doubt your simulator's capability, accuracy and speed. It's
just that in this case you'll get the wrong answer faster.=20
regards,
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC
Pratt, Gary wrote:=20
=3D20
Perry,
=09
Good to hear your are using ICX. That tool supports both the
fast AMS
models and fast s-parameter models. It would have also been
good if you
were using Xilinx V4. Unfortunately, for the previous
generation of
FPGA, the AMS behavioral model you are thinking of is probably
the one
from the Xilinx competition. =3D20
=09
Fortunately, V2 is rather straightforward technology. I could
provide
you with a somewhat similar model, and show you to modify it to
match
the characteristics of V2. The most complicated part is setting
up the
SPICE simulations to extract the characteristics from the
transistor-level models. I can send you the testbenches we used
for a
PCI Express driver, which I'm sure you could adapt to extract
the
characteristics and make to make a model for any particular V2
configuration (I'd suggest leaving the full-functional,
all-configuration model for a later exercise). =3D20
=09
Gary
=09
Btw: your Mentor AE (Tony Dunbar) pinged me offline and
indicated he
would be willing to help (though, the last third of q4 is always
a
particularly busy time for the AEs)=3D20
=09
=09
=09
=3D20
=09
=09
-----Original Message-----
From: Perry Qu [mailto:perry.qu@xxxxxxxxxxx]=3D20
Sent: Tuesday, November 29, 2005 1:06 PM
To: Pratt, Gary; 'si-list'
Subject: RE: [SI-LIST] Re: Bit pattern for high speed serial
link
simulation
=09
Gary:
=09
Thanks for your suggestion. I'm interested in more details of
AMS model.
Currently we use heavily Mentor SI tool for general board
simulation
(ICX and ePD) but we still use HSPICE for Gbps stuff. =3D20
=09
The device I'm referring to is Virtex II Pro Rocket I/O. I
roughly
remember that Xilinx provide some type of behavior model for ICX
but not
sure whether this is what you are referring to. Please let me
know.
=09
Regards
=09
Perry
=09
=09
=09
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=09
Perry Qu=3D20
=09
Design & Qualification, Alcatel Canada=3D20
=09
600 March Road, Ottawa ON, K2K 2E6=3D20
=09
DID: 613-7846720 Fax: 613-5993642=3D20
=09
Email: perry.qu@xxxxxxxxxxx=3D20
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=09
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Pratt, Gary
Sent: Tuesday, November 29, 2005 12:37 PM
To: Perry.Qu@xxxxxxxxxxx; si-list
Subject: [SI-LIST] Re: Bit pattern for high speed serial link
simulation
=09
Perry,
=09
With an AMS model and an AMS-SI simulator, you could simulate
your
PRBS15 pattern in an hour or so. And, you wouldn't need to be
concerned
with the loss of crosstalk or non-linear driver information
which are
characteristic of many frequency-domain channel analysis
techniques.
With an AMS model, you could also investigate the effects of PLL
jitter
and other sampling effects. And, you could simulate the
non-deterministic jitter to investigate any possible jitter
amplification caused by the channel. Plus, you could add
automated
measurements to accelerate your analysis process. Plus ...
=09
I'll be delivering a half-day tutorial on AMS and IBIS 4.1 at
DesignCon
February 6 if you are interested. Could also do a 45-minute
WebEx
summary if you have enough interest at your company. =3D3D20
=09
To gain the full benefit of the AMS model speed, it is also
important to
use a simulator which uses analytical integrals for fast and
accurate
time-domain analysis of the s-parameter package and channel
models.
There is also a session at DesignCon which touches on this
(session
5-WA2, Wednesday, 9:40 AM). =3D3D20
=09
I can also help you work with your silicon provider to develop
the AMS
models, if that would be helpful.
=3D3D20
=09
Gary
=09
=09
=09
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Perry Qu
Sent: Monday, November 28, 2005 4:00 PM
To: 'steve weir'; 'si-list'
Subject: [SI-LIST] Re: Bit pattern for high speed serial link
simulation
=09
Steve:
=09
Thanks for the suggestion. This is through encoder. I'm running
a PRBS15
pattern simulation right now (already a week) and I do noticed
closure
of eye mask due to the pattern. May try an even longer pattern
but the
simulation in hspice is just too slow. Will probably look into
Allegro
PCB SI channel analysis tool.
=09
Regards
=09
Perry
=09
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D=3D
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=3D3D3D=3D3D
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3D3D=3D3D3D=3D3D3D=3D3D3D=3D3
D=3D
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=09
Perry Qu=3D3D20
=09
Design & Qualification, Alcatel Canada=3D3D20
=09
600 March Road, Ottawa ON, K2K 2E6=3D3D20
=09
DID: 613-7846720 Fax: 613-5993642=3D3D20
=09
Email: perry.qu@xxxxxxxxxxx=3D3D20
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-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Monday, November 28, 2005 4:26 PM
To: Perry.Qu@xxxxxxxxxxx; si-list
Subject: Re: [SI-LIST] Bit pattern for high speed serial link
simulation
=09
Perry, if you are bypassing the encoder/decoder, then PRBS7
generates
sufficient run-length. If you are driving the encoder, you want
a run
length > 15, so PRBS21 or PRBS31 would be a better choice.
=09
Steve.
At 03:21 PM 11/28/2005 -0500, Perry Qu wrote:
=20
Hi,
=09
What will be a realistic bit pattern to use for
simulation of a=3D20
serial=3D3D20 link
(3Gbps) with 8B/10B encoding ? Right now I used PRBS7
pattern but=3D20
I'm=3D3D20 not sure whether it captured the worst case
pattern compared=3D20
to=3D3D20 reality, where the live data traffic is a lot
more random. =3D
=20
8B/10B
=09
=20
has a
=20
=09
=20
run length of 5 but if it's fed with say a PRBS31 bit
stream, will =3D
=20
I=3D3D20
=09
=20
get more spectrum peaks than just a pure PRBS7 pattern
without encoding
=20
=09
=20
which repeat itself every
127 bits ?
=09
Thanks
=09
Perry
=09
=09
=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D=
3D3D=3D3D3D=3D3D3D=3D3D3D=3D3
D=3D
=20
3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3
=20
D=3D3D
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=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D=
3D3D=3D3D3D=3D3D3D=3D3D3D=3D3
D=3D
3D
=20
Perry Qu
=09
Design & Qualification, Alcatel Canada
=09
600 March Road, Ottawa ON, K2K 2E6
=09
DID: 613-7846720 Fax: 613-5993642
=09
Email: perry.qu@xxxxxxxxxxx
=09
=09
=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D=
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3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3D=3D3D3
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3D3D=3D3D3D=3D3D3D=3D3D3D=3D3
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