[SI-LIST] Re: Behavioral modeling
- From: "Donnelly, Mike" <mike_donnelly@xxxxxxxxxxx>
- To: "'arpad.muranyi@xxxxxxxxx'" <arpad.muranyi@xxxxxxxxx>,"'panch_si@xxxxxxxxx'" <panch_si@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Tue, 22 Jul 2003 12:15:52 -0700
Arpad and Panch,
In the document referenced, there are a number of restrictions on the use of
the LVDS IBIS model. For example, it states that for accuracy, the same VDDQ
and the same loading conditions must be present as when the model was created.
This is a rather severe restriction, as it practically defeats the intent of a
simulation model (i.e. to predict performance under uncertain operating
conditions). I believe the fundamental problem is that IBIS assumes a specific
Output topology (i.e. pull-up and pull-down elements, with drive strengths
specified as i vs. v data). If the actual circuit being modeling has a
fundamentally different topology, such as a controlled current source being
steered from one output pin to the other, then it will be very difficult to
match results under widely varying operating conditions.
Beyond matching the basic Output electrical characteristics, there is
additional complexity in today's multi-gigabit I/O designs that must be
included for accurate system performance evaluation. This includes pre-emphasis
control logic, settable or adaptive equalization characteristics, digitally
controlled termination impedance, etc. Even the PLL tracking capability of the
Clock and Data Recovery (CDR) System has a significant impact on overall system
performance (i.e. jitter and BER), and should be included in the system level
analysis.
The need to handle these types of complex I/O buffer behaviors is what drove
the recent extension to the IBIS Standard (Bird 75). The IBIS Committee wisely
discerned that the rapid advancement of I/O technology could not be dealt with
via piecemeal behavioral extensions to the IBIS Specification. So they opened
the doors to existing hardware modeling standards: Currently SPICE and
VHDL-AMS. SPICE, of course, is a well known and established format for
describing any general circuit structure. VHDL-AMS is a newer analog and
mixed-signal modeling standard (IEEE 1076.1), specifically designed to meet
complex behavioral modeling requirements, such as those of multi-gigabit I/O
technology. Because it provides "behavioral modeling", like IBIS, it protects
the vendor's circuit structure "IP", and also simulates very fast. Its
capability to model all of the advanced features described above (i.e. current
mode signaling, pre-emphasis and equalization, CDR, etc.) has been
demonstrated. http://www.mentor.com/systemvision/high_speed/index.html
<http://www.mentor.com/systemvision/high_speed/index.html>
Although there is somewhat limited support for this technology today, that is
changing quickly. Many IC vendors have expressed strong interesting in using
VHDL-AMS for capturing and distributing their current and next generation
multi-gigabit I/O technology, and several EDA tool vendors have or are
developing capability to support this format. Because it is a technology that
perfectly addresses an important and growing need, I expect its widespread
adoption to come rapidly. Perhaps this is similar to the early days of IBIS?
Mike
-----Original Message-----
From: Muranyi, Arpad [mailto:arpad.muranyi@xxxxxxxxx]
Sent: Monday, July 21, 2003 3:35 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Behavioral modeling
It can be done (if you know what you are doing)...
Have you seen this presentation?
=20
http://www.eda.org/pub/ibis/summits/jun03b/haller.pdf
=20
Arpad
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D
-----Original Message-----
From: Panch Chandrasekaran [mailto:panch_si@xxxxxxxxx]
Sent: Monday, July 21, 2003 3:12 PM
To: Muranyi, Arpad; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Behavioral modeling
Arpad,
Thanks for your reply. There is a general feeling that IBIS is not very =
accurate for multi-gigabit/s data streams and it is a pain to =
incorporate features like pre-emphasis etc. Any thoughts on this.=20
=20
Panch
"Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx> wrote:
Have you checked into IBIS modeling?
http://www.eigroup.org/ibis/ibis.htm
Arpad
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
-----Original Message-----
From: Panch Chandrasekaran [mailto:panch_si@xxxxxxxxx]
Sent: Monday, July 21, 2003 11:22 AM
To: si-list@xxxxxxxxxxxxx
Cc: panch_si@xxxxxxxxx
Subject: [SI-LIST] Behavioral modeling
All,
What is a good way to do behavioral modeling? Running SPICE for high =3D
speed simulations ( 3 - 4 Gbps) can be very time consuming especially =
=3D
with backplane,via, connector models etc. I have heard that VHDL AMS and =
=3D
Cadence's DML are options that can used with their tools. Is there a =3D
simpler way to do it with reasonable accuracy?
Stuff that can be imported into SPICE tools and that will save on =3D
simulation times.
=3D20
Thanks for your thoughts.
=3D20
Panch Chandrasekaran
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