[SI-LIST] Re: Arguments against Thevenin bias/termination for ddr2 Vtt
- From: agathon <hreidmarkailen@xxxxxxxxx>
- To: si-list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 May 2007 11:39:10 -0700
My apologies to Bill for doubting him and being blinded by science... :-)
I stand justly rebuked.
Many thanks to all......
Steve, sorry to query for detail... maybe there's a quick ref. you can point
to?
in #2 answer do you mean extend a very wide finger or shape instead of using
the solid plane?
I realize this wouldn't necessarily be a hard rule.
#3: Thev. term. reduces cavity Q? Can you suggest a Spice setup to show
this? I don't see how there's any added R series to the cavity. Or, it's
just due to the added Thev. vias, or the loop with 100ohms - instead of Vtt
regulator with the lower Z whole signal path?
#4: "In the Thevenin case you get much less signal crosstalk for equivalent
bypass impedance as with the end termination into Vtt."
Due to less delta-i from Vddq I suppose, due to divider? We aren't using
series R. I assume you're implying that each termination requires its own
decap for best results (?).
#5: -----
#6: But here you mention "shared bypass" as a potential helper. I see, just
happens to reduce delta-i through nearest cap (?). Ie: data dependent.
Overall, I seem to get from the replies: Use separate large shape from vdd
for vddq to Thevenin terminations. The shape branches off from a point
close to vdd at ctlr, since it is tx for Addr/Cmd signals. Ie: As jedec
specifies, Vtt & Vref must track Vddq of tx. Larger decap at branch.
Added decap per termination, right at divider.
On 5/29/07, steve weir <weirsi@xxxxxxxxxx> wrote:
>
> Agathon I mostly agree with Bill here. Taken point by point:
>
> 2. The PDN (Vddq) is used dc-coupled, so its behavior statistically
> influences Vtt. That is, Vtt is more subject to Vddq and other noise.
>
> Not necessarily so. It depends on how you do the board layout and bypass
> for Vddq in the Vtt area. In the ideal case Vddq from the transmitter
> forwards to the Vtt divider island. In that case Vtt tracking against the
> actual switching signals which is what we want can be better than a fixed
> Vtt, ie lower jitter.
>
> 3. Vtt is then subject to board PDN resonances.
>
> Only if you have one giant cavity AND that cavity has resonance
> issues. As Bill infers if you have a significant resonance issue, that's a
> problem you probably need to fix anyway. The Thevenin case has a tendency
> to reduce cavity Q.
>
> 4. The Thevenin method makes Vin (rcvr) more sensitive to Vddq noise
> merely
> from the linear network analysis point of view, or to Vtt offset at worst
> case pullup/down values, than when Vtt is regulated and terminated with 50
> ohms (nom.). ... I'm verifying this now; may not be true. I assume 1%
> resistors.
>
> At anything like the bit rate, whether you use a linear supply or not the
> bypass scheme controls the noise. In the Thevenin case you get much less
> signal crosstalk for equivalent bypass impedance as with the end termination
> into Vtt. As mentioned before, whether or not other noise on the board
> impacts the local Vddq is a design issue.
>
> 6. Vtt current switching noise is injected into the PDN. Not very nice if
> layout or margins are poor.
>
> A bad design is still a bad design. Under the right circumstances a bank
> of Thevenin terms could send one over margin, but it could for reasons
> stated above just as likely pull a design that is out of margin back in due
> to the increase in shared bypass and improved damping. Either way the
> design is done properly, or life is bad. If the design is better off
> isolating Vddq in the region of the terminations, that is an easy task.
>
> Steve
>
>
> agathon wrote:
> > Bill,
> > au contraire, mon frere....
> >
> > #2-4, 6 are also specific to the Thevenin bias/termination, as opposed
> to
> > Vtt separate regulator.
> >
> > Come on, you frikkin experts. :-) This should be easy. I double
> dare
> > ya.
> >
> >
> >
> > On 5/29/07, Bill Owsley <wdowsley@xxxxxxxxx> wrote:
> >
> >> Only one and five are accurate. The rest are symptoms of other
> problems
> >> that should have been addressed.
> >>
> >>
> >> *agathon <hreidmarkailen@xxxxxxxxx>* wrote:
> >>
> >> Hello,
> >> Assume a 50 ohm environment so, for example, a 100 ohm pullup to Vddq (
> >> 1.8V)
> >> and pulldown to gnd, for Address/Command signal group.
> >> The typical method is to use a lin. regulator with outputs for Vref and
> >> Vtt,
> >> so they supposedly track each other better.
> >>
> >> The only arguments against the pullup/down I can come up with are:
> >>
> >> 1. Extra dc current (but the regulator has Vout-Vin losses, too). For
> >> Addr./Cmd it's around 200mA. for a single port, and doesn't increase w/
> >> memory size.
> >> 2. The PDN (Vddq) is used dc-coupled, so its behavior statistically
> >> influences Vtt. That is, Vtt is more subject to Vddq and other noise.
> >> 3. Vtt is then subject to board PDN resonances.
> >> 4. The Thevenin method makes Vin (rcvr) more sensitive to Vddq noise
> >> merely
> >> from the linear network analysis point of view, or to Vtt offset at
> worst
> >> case pullup/down values, than when Vtt is regulated and terminated with
> 50
> >> ohms (nom.). ... I'm verifying this now; may not be true. I assume 1%
> >> resistors.
> >> 5. Uses more pcb space and routing area.
> >> 6. Vtt current switching noise is injected into the PDN. Not very nice
> if
> >> layout or margins are poor.
> >>
> >>
> >>
> >> Arguments in favor:
> >> 1. Using Vddq actually may force Vtt to track it better. Regulators
> >> providing Vtt and Vref (with Vddq sense) cannot track Vddq as quickly
> or
> >> accurately.
> >> 2. The dc current penalty is small.
> >> 3. ???
> >>
> >>
> >>
> >> Thanks very much.
> >>
> >> -----------
> >>
> >>
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