[SI-LIST] About the DDR2 Data Timing Budget Calculation
- From: "YangJeffrey" <steam189759@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 19 Apr 2006 16:57:13 +0800
when I calculate the DDR2 data setup and hold margin, I use the formula(Write
Case, have not included crosstalk and ISI effect):setup margin =
Tsetup_controller_output - Tdata_delay_max + Tdqs_delay_min - Tsetup_receiver
delay max is measured to the Vih(when rise)delay min is measured to the
Vil(when rise)
I think that the interconnect timing budget should include the skew measured
between Vil and Vih.
But in Micron document:Micron DDR2-533 Memory design guide for two-DIMM
unbuffered systems, the DDR2 Write Budget is estimated in the table below:(You
can also download it from website:
http://download.micron.com/pdf/technotes/ddr2/tn_47_01.pdf)
ELEMENT KEW COMPONENT SETUP HOLD UNITS
Transmitter Total Skew at Transmitter 325 325 ps
Clock Data/Strobe PLL jitter 25 25 ps
DRAM device tDH/tDS 100 225 ps
total Device 350 350 ps
Interconnect XTK (cross talk) - DQ 55 55 ps
XTK (cross talk) - DQS 40 40 ps
ISI - DQ 30 30 ps
ISI - DQS 5 5 ps
Input Capacitance Matching 25 25 ps
REFF Mismatch 10 10 ps
Input Eye Reduction (VREF) 25 25 ps Path Matching
(Board) 25 25 ps
Path Matching (Module) 10 10 ps Total Interconnect
Interconnect Skew 225 225 psTotal Budget 1875/2 @ 533 MHz
937.5 937.5 psTotal Budget Consumed by Controller and DRAM
Transmitter + DRAM + Interconnect 925 925 psInterconnect Budget
Total-(Transmitter + DRAM + Interconnect) 12.5 12.5 ps
It seemed that the interconnect budget data in the table do not include
the skew caused by Vil and Vih. If considering the skew caused by Vil and Vih,
the interconnect budget will be negative.Can the skew caused by Vil and Vih be
ignored orit has been included in the the total interconnect skew in the table?
Thanks,Jeffrey Yang
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