[SI-LIST] AW: Re: PCB via simulations

  • From: "Thomas Beneken" <beneken@xxxxxxxxxxxx>
  • To: <DSWANSON@xxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 1 Apr 2002 16:00:04 +0200

Hi Dan,

ok, simulators need a restricted calculation volume, because mems resourc=
es
are restricted too. One can select a perfect conducting box or a free spa=
ce
boundary box. You may want the box far enough from your objects of intere=
st.
(This is the week point in Kevins setup: really far enough?)

I don't want to defend Kevins paper, but I've seen power planes in his
model. This is his layer stack:

18.5 mils      -------------------------------- perfect conducting bounda=
ry
box
               |p1            via             |
13 - 13.5 mils |->-------------|              | trace 1
11 - 11.5 mils --------------- | -------------| power plane
               |                              |
 7 -  7.5 mils --------------- | -------------| ground plane
 5 -  5.5 mils |               |------------<-| trace 2
               |                            p2|
 0             -------------------------------| perfect conducting bounda=
ry
box

He defined discrete ports between the ends of the traces and where the
planes meet the bounding box ("currents wrap around"). Looks quite ok for
me. Dan, please have a second look and correct me if I'm wrong. I admit a
wider bounding box would be better (I do have a Gigabyte-RAM workstation).

Regards, Thomas

-----Urspr=FCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]Im Auftrag von Dan Swanson
Gesendet: Montag, 1. April 2002 14:44
An: 'beneken@xxxxxxxxxxxx'; si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Re: PCB via simulations



It looks like the boundaries of the
simulation space are perfectly conducting
walls. They might also be some kind of
low impedance absorbing boundaries.

In either case, there is no path for return
current in this model, other than the walls
of the simulator. This is a common mistake
is em simulation of multilayer transitions.
The results will be overly optimistic. In a real
board, the return path will typically be some
random combination of ground vias near this
signal via.

Dan

Dan Swanson             EMAIL:  d.swanson@xxxxxxxx
Forem USA                       PHONE:          978-834-4085
37 South Hunt Road      FAX:    978-388-7077
Amesbury, MA  01913


-----Original Message-----
From: Thomas Beneken [mailto:beneken@xxxxxxxxxxxx]
Sent: Monday, April 01, 2002 7:10 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCB via simulations


Hi All,

I ran across PCB via simulations by Kevin Thomas of Cray Inc., September
1997. Updated March 2001.
http://lc.cray.com/apps/xvia/

hope it's useful for someone, (lost that thread ...)

Thomas


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