[SI-LIST] AW: PCIe3 trace width(8mil) and edge distance(3 to 4 mil) between + and - of differential pairs?
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 13 Jan 2011 08:38:21 +0100
there have been many discussions on the list about the coupling, thus I don't
want to summarize all of them.
For your special case I see a potential issue in close coupling as it is on the
outer layer. Outer layer aren't preferred for impedance controlled traces as
(among other reasons) the copper thickness added during thru hole plating is
hard to control. This leads to etching variations. With such close coupling as
you propose (3-4 mil) you will see strong impedance variations ( I would expect
the gap to vary at least from 3 to 5 mil).
Ask your PCB vendor about the etch tolerances for your layout and stack, and
then do a quick cornercase simulation.
BR
Gert
--------------------------------------------------------------------------
Absender ist HARTING Electronics GmbH & Co. KG; Sitz der Gesellschaft:
Espelkamp; Registergericht: Bad Oeynhausen; Register-Nr.: HRA 5596; persönlich
haftende Gesellschafterin: HARTING Electronics Management GmbH; Sitz der
Komplementär-GmbH: Espelkamp; Registergericht der Komplementär-GmbH: Bad
Oeynhausen; Register-Nr. der Komplementär-GmbH: HRB 8808; Geschäftsführer:
Edgar-Peter Duening, Torsten Ratzmann, Dr. Alexander Rost
-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Dong Kim
Gesendet: Mittwoch, 12. Januar 2011 19:44
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] PCIe3 trace width(8mil) and edge distance(3 to 4 mil)
between + and - of differential pairs?
Hi,
I have 8 lane differential PCIe3 (8Gbps) signals to be routed between a BGA
component and PCIe3 edge connector on a some FR4 material board.
The distance between the ball and the edge connector pin is about 2 inches. No
via on the top layer RX pairs and one via with 0402 capacitors on the bottom
layer TX pairs.
I am using 8 mil traces width with matching 100 ohm differential impedance at
the receiver chip for 50ohm board impedance. The distance between the edges of
the "+" signal and "-" signal is 3 to 4 mil. It is close coupling. I expect
there will be some mutual coupling between the edges.
In my past projects with high speed differential signals, I always used loose
coupling between + and - signals of a differential pair.
I am curious of the potential issues by using close coupling between the + and
- of the pairs.
The reason for close coupling is not for the concern of the potential EMI issue.
I understand board level high speed differential signals does not have EMI
issues like actual transmission cables running up on the air.
If you see a potential issue for close coupling, please let me know.
Simulation will be performed.
But, in my opinion, simulation is only as good as the tool and the parameter
can go.
I thouught it would be good idea to get some theoretical concept bounced around.
Thanks,
Dong S. Kim
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
- » [SI-LIST] AW: PCIe3 trace width(8mil) and edge distance(3 to 4 mil) between + and - of differential pairs? - Havermann, Gert
