[SI-LIST] Re: AC cap placement on Clocks
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "wolfgang.maichen@xxxxxxxxxxxx" <wolfgang.maichen@xxxxxxxxxxxx>
- Date: Fri, 23 Oct 2009 09:44:12 -0700
A very simple thing to do is to test a real line with AC capacitors in it
with a TDR and see how much signal degradation there is. Then, if there is
any significant degradation, something can be investigated for reducing the
degradation. I've done this as have others, and the degradation is not
significant and certainly not worth all the words that have been thrown at
the subject these last few days.
But, then, maybe some people are paid by the word!
Sometimes a test is worth a thousand words! Not unlike a picture.
Lee Ritchey
> [Original Message]
> From: <wolfgang.maichen@xxxxxxxxxxxx>
> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
> Cc: Sam Pete <cygnul@xxxxxxxxx>; icer world <icermail@xxxxxxxxx>;
<si-list@xxxxxxxxxxxxx>; <si-list-bounce@xxxxxxxxxxxxx>
> Date: 10/22/2009 10:18:01 AM
> Subject: [SI-LIST] Re: AC cap placement on Clocks
>
> Hello Sam,
> an ideal capacitor will be completely transparent and high-frequency
> signal (down to the cutoff frequency - the capacitor C in combination
with
> the Thevenin-equivalent line impedance of 2*Zo form a high-pass filter
> with a time constant of 2*Zo*C). So from that standpoint it does not
> matter at all where you place it, as Lee already stated.
>
> Of course a real capacitor always has some parasitic package and mounting
> inductance, so if you go to very high frequencies or data rates
> (multi-Gbit/sec) you will end up seeing reflections caused by that.
> Although at your speeds (below a GHz) that won't be an issue unless you
> reeally mess up the design (e.g. use a through-hole capacitor instead of
a
> good surface mount ceramic one). In that case it will be better in
improve
> your design rather than try to find a "sweet spot" for the placement
which
> will make your design very sensitive against any changes (e.g. line
> length, other parasitics). Failing that, the best bet is probably to
place
> it very close (within ~1/4th of the shortest wavelength of interest,
given
> by the frequency 0.33/rise_time) to either your driver or your receiver.
>
> The second consideration would be whether you put in the AC coupling
> purely for signaling reasons (e.g. to avoid debiasing driver or
receiver),
> or whether it shall also act as protection. If e.g. it shall protect the
> driver against short circuits (e.g. if driver and receiver reside on
> different boards that get hot-plugged together), it may be better to
place
> the cpacitor on the driver side. But that willd depend on the specific
> design.
>
> Wolfgang
>
>
>
>
>
>
> "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
> Sent by: si-list-bounce@xxxxxxxxxxxxx
> 10/22/2009 06:39 AM
>
> To
> "icer world" <icermail@xxxxxxxxx>, "Sam Pete" <cygnul@xxxxxxxxx>,
> si-list@xxxxxxxxxxxxx
> cc
>
> Subject
> [SI-LIST] Re: AC cap placement on Clocks
>
>
>
>
>
>
> Form an SI point of view, it does not matter where along the path the
> capacitors are placed.
>
>
> > [Original Message]
> > From: icer world <icermail@xxxxxxxxx>
> > To: Sam Pete <cygnul@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> > Date: 10/21/2009 8:48:26 PM
> > Subject: [SI-LIST] Re: AC cap placement on Clocks
> >
> > It's hard to say where the AC cap should be placed ,so you'd better do a
> simulation if you have device models .
> > I'm in doubt that why you use the AC coupling manner since the driver
> and
> the receiver are both LVDS level.
> >
> >
> >
> > ________________________________
> > From: Sam Pete <cygnul@xxxxxxxxx>
> > To: si-list@xxxxxxxxxxxxx
> > Sent: Thu, October 22, 2009 7:22:17 AM
> > Subject: [SI-LIST] AC cap placement on Clocks
> >
> > Hi All,
> > I have a situation like this:
> > LVDS Driver, ac cap, LVDS receiver (internal term) 156MHz clock.
> > |>-----------------||----------------|>
> > |>-----------------||----------------|>
> >
> >
> > What is the optimum place to put coupling cap when the clock is
> ac-coupled.
> > Should it be close to driver or should it be close to receiver.
> >
> > From my understanding, the discontinuity should not be visible to the
> electrical length of the signal. Having said that, ac cap should be as
> close as possible to Driver.
> >
> > please share your thoughts.
> >
> > Thanks
> > Sam
> >
> >
> >
> >
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