[SI-LIST] Re: AC cap placement on Clocks
- From: icer world <icermail@xxxxxxxxx>
- To: Sam Pete <cygnul@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Wed, 21 Oct 2009 20:48:26 -0700 (PDT)
It's hard to say where the AC cap should be placed ,so you'd better do a
simulation if you have device models .
I'm in doubt that why you use the AC coupling manner since the driver and the
receiver are both LVDS level.
________________________________
From: Sam Pete <cygnul@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Thu, October 22, 2009 7:22:17 AM
Subject: [SI-LIST] AC cap placement on Clocks
Hi All,
I have a situation like this:
LVDS Driver, ac cap, LVDS receiver (internal term) 156MHz clock.
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What is the optimum place to put coupling cap when the clock is ac-coupled.
Should it be close to driver or should it be close to receiver.
From my understanding, the discontinuity should not be visible to the
electrical length of the signal. Having said that, ac cap should be as close
as possible to Driver.
please share your thoughts.
Thanks
Sam
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