[SI-LIST] Re: A question about clock EMC
- From: "DAVID CUTHBERT" <telegrapher9@xxxxxxxxx>
- To: jasonleehan@xxxxxxxxx
- Date: Tue, 1 Jan 2008 20:34:33 -0700
Han Li,
you can model this accurately in SPICE and explore it. Using the SPICE FFT
feature you can examine the frequency spectra. I modeled what I think your
system looks like using a shunt 6.8 - 12 pF capacitor having a series
inductance of 2 nH. The driver is a CMOS driver having a rise time of 350 ps
and a series inductance of 4 nH. There are two places that I measured the
current: The RF current in the driver and the RF current flowing in the
receiver.
In any event, I see that some frequencies are improved and some are made
worse by the addition of the capacitor. And the signal integrity is
definitely harmed by the poor impedance match caused by the capacitor.
However, if the signals at the receiver are such that they are 'legal'
signals under all conditions with the capacitor then the system should work
just fine. You could leave pads on the PCB to add the caps (or remove
them) if your board fails EMC. The downside is the additional board area
required.
Dave Cuthbert
SI/EMC Consultant (and all analog design from low noise to 100's of kW.
Antennas too)
On Jan 1, 2008 6:48 PM, Han Li <jasonleehan@xxxxxxxxx> wrote:
> Hi, experts.
> I am doing a board design, on which I have a 66MHz (3.3V), and a
> 25MHz(3.3) oscillator. I used seriese termination for these clock lines.
> topoloy like this
> [A]--[seriesRes]----------long line-------------[Load]
> [A] is clock source, then resistor , then transmission line ,then load at
> end.
> But our EMC consultant recommended me to add a cap between series Resi and
> GND. The cap and resistor are located very close. so topoloy now like
> this:
> [A]----[seriesRes]----------long line-------------[Load]
> |
> ----
> ---- ( capacitor)
> |
> GND
> He didnot recommentd cap's value, only said it may help EMC test.
> I understand that such a cap can increase clock rising time and reduce
> frequency spectra. BUT, donnot we creat a matched transmission line using
> series resistor? Why intentionally add a cap to destroy such a matched
> line?
> Can I really get a good EMC result?
> Could anyone provide a deeped and more detailed explanation on this?
> Thank you very much.
>
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