Hi All, I've been developing a new Open Source (GPLed) SI Analysis tool. Eventually I would like it to be able to accurately simulate "medium-speed" PCB level SI with topologies composed of simple passive termination and t-lines between IBIS defined devices. I'm currently soliciting help, bug-reports, suggestions, and comments from interested folks and thought that this would would be a good place to look. Maybe someday it will have a fancy GUI, Windows installer, etc. but for now it is a source code only distribution that runs on Linux, or on Windows using cygwin. It's a Python module so requires a Python Interpreter (uses Python instead of a spice-like scripting language). It's currently an alpha release with very basic functionality. If you're interested you can find it here: http://www.thedigitalmachine.net/eispice.html Please don't respond to this email on this list for help setting up / running the tool. I would like to avoid annoying subscribers to this list that aren't interested. I've setup a dedicated mailing list that you can join from the webpage above for discussion related to this tool. Thanks! Charles ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu