Hello, In the Infiniband and PCI Express electrical specifications the Eye opening diagrams/templates are created with 4 vertex quadrilaterals (diamonds). Furthermore, the UI math works out as I would expect, that is: 1UI =3D Eye-opening-min + Jtr Conversely, the XAUI (803.3ae) and RapidIO electrical specs use 6 vertex hexagons. Refering to 802.3ae section 47 terminology, I see how the X1 and 1-X1 vetices are placed, they in fact obey the 1UI =3D Eye-opening-min + Jtr relationship I observed above. I do not see how the X2 and 1-X2 vertices are derived, do you know how these vertices are derived from the Tx or Rx UI specs? I tried a transition time calculation but it did not work out (but of course my calculations may be incorrect). Thx, Jim - Jim Antonellis jim.antonellis@xxxxxxxxxxxxx Sandburst Corp www.sandburst.com Office: 978.689.1669=20 Cell: 978.618.4745 This message and any attachments are Confidential and may be Legally Privileged. It is intended solely for the addressee. If you are not=20 the intended recipient, please delete this message from your system=20 and notify us immediately. Any dis-closure, copying, distribution or=20 action taken or omitted to be taken by an unintended recipient in=20 reliance on this message is prohibited and may be unlawful. =20 ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu