Am 18.06.2013 11:59, schrieb David Given:
Yes, this certainly is L2 cache. I think, the first thing which bootcode.bin does after dram initialization is to somehow write the cache contents into dram. At least I think I have seen something like this.[resend due to MUA weirdness. Sorry about the lateness] On 09/06/13 14:30, Scott Mansell wrote:There is also some ram at0x60008000 which bootrom uses for it's stack and bootcode.bin uses as a temporary place to copy and run code which touches various registers that configure the L1 and L2 caches.After spending quite a lot of time trying to figure out why my receive code appears to be truncating files, I have discovered that this block of memory has a read-only section from 0x600080d4 to 0x60008214. I hope this information is useful to someone... (The RAM is also mirrored every 0x800 bytes from 0x60008000 to 0x6000b800.) The data sheet describes a 'coarse-grained MMU used to map ARM physical addresses onto system bus addresses', which also appears to be used at the VC4 MMU. Is anything known about this? I have also noticed that: - the 128kB block of memory that bootcode.bin is loaded into is mapped at 00000000, 40000000, 80000000, but not at c0000000. The rest of the SDRAM range isn't accessible. I am wondering whether this 128kB block is actually the cache in a funny mode.
- everything from 60000000 to 7dffffff appears to returns zeros (I haven't look at all of it, obviously). This is *not* mirrored elsewhere. The boot ROM, the mysterious RAM at 0x60008000, and the even more mysterious non-RAM at 0x600080d4 is layered on top of this, whatever it is. The only conclusions I've come to is that (a) the memory architecture is stranger than it first looked and (b) I need to go to bed.