> There is an errata for the 9301 which includes a > claim of instability with auto-precharge at SDRAM > bus frequencies in excess of 50Mhz: > > http://www.cirrus.com/en/pubs/errata/er636c1.pdf > > Does this relate to the condition you describe? No. Thats a completely different problem. The problem is in SDRAM initialization, auto-precharge is a controller mode that has the potential to increase SDRAM speed by saving an explicit SDRAM precharge cycle on the bus. There is a multi-step procedure you have to follow explicitly to properly initialize SDRAM. One of those steps is a PRECHARGE-ALL operation which will precharge (close) all open banks. The EP93xx datasheet says that by having only the INIT and CKE bit set in the GICONFIG register will issue a PRECHARGE-ALL bus cycle-- it doesn't. Way back before when we caught this on the logic analyzer and devised our workaround, this was causing our POST SDRAM test to fail randomly by clobbering the first 4-16 SDRAM reads/writes out of reset. Certain SDRAM chips were more or less susceptible to not being properly initialized. It is impossible to get a 100% up-to-spec SDRAM initialization without a PRECHARGE-ALL bus-cycle. //Jesse Off