[linux-cirrus] Re: SDRAM initialisation
- From: Jean-Philippe Francois <jp.francois@xxxxxxxxxx>
- To: linux-cirrus@xxxxxxxxxxxxx
- Date: Wed, 09 Feb 2005 18:01:42 +0100
Strange bug indeed !
Is this bug present on all CPU revision (D0 and D1, I don't know if E0
is available yet) ?
JP Francois
On Wed, 2005-02-09 at 17:10, Jesse Off wrote:
> The multiple loads of the mode register look strange to me too. You should
> only need to load the mode register once per chip, so e.g. if you have 4
> chip selects being used, you have to emit 4 load mode register operations.
>
> Note that there is an as-of-yet undocumented Cirrus chip errata we at
> Technologic Systems found back in October. It turns out that the SDRAM
> initialization operation for emitting the "PRECHARGE-ALL" does not actually
> emit a PRECHARGE-ALL on the sdram bus. I would urge everybody designing
> this chip in to contact their rep about this as it seems they really want to
> keep this bug quiet. There is a kludgy software workaround we figured out
> they should be able to give you.
>
> //Jesse Off
>
>
> > Hi,
> >
> > I am looking at the SDRAM initialisation in U-boot.
> > For the EDB9312 board, here is how the Mode register
> > is set :
> > mov r1, #0x0008800
> > ldr r0, [r1]
> >
> > ldr r1, =0x0400000
> > ldr r0, [r1]
> >
> > ldr r1, =0x0808800
> > ldr r0, [r1]
> >
> > ldr r1, =0x0c08800
> > ldr r0, [r1]
> >
> > According to the user guide, when MRS is set, bit 23-10 of the read
> > address are sent in the mode register of the SDRAM.
> > What is the use of doing multiple read, since each read will erase the
> > previous one ?
> >
> > According to the user guide only one mode is supported :
> > it's CAS=3, Burst length = 4, sequential mode, use burst write,
> > which should translate in the following command :
> >
> > mov r1, #0x000c800
> > ldr r0, [r1]
> >
> > (See user manual p 459, under table 12.7)
> >
> > I am probably missing something here, so any light is welcome.
> >
> > Regards,
> >
> > JP Francois
> >
> >
> >
> >
>
>
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